PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 108

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC24FJ64GB002-I/SS
0
PIC24FJ64GB004 FAMILY
8.1
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
• Secondary Oscillator (SOSC) on the SOSCI and
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal USB PLL block, which
generates both the USB module clock and a separate
system clock from the 96 MHz PLL. Refer to
Section 8.5 “Oscillator Modes and USB Operation”
for additional information.
The Fast Internal RC (FRC) provides an 8 MHz clock
source. It can optionally be reduced by the pro-
grammable clock divider to provide a range of system
clock frequencies.
The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc-
tion cycle clock, F
cycle clock is also denoted by F
instruction cycle clock, F
OSCO I/O pin for some operating modes of the primary
oscillator.
TABLE 8-1:
DS39940D-page 108
Fast RC Oscillator with Postscaler
(FRCDIV)
(Reserved)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator
(SOSC)
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL Module
(FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
OSCO pins
SOSCO pins
2:
CPU Clocking Scheme
Oscillator Mode
OSCO pin function is determined by the OSCIOFCN Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
CY
. In this document, the instruction
OSC
/2, can be provided on the
OSC
/2. The internal
Oscillator Source
Secondary
Primary
Primary
Primary
Primary
Primary
Internal
Internal
Internal
Internal
Internal
Configuration
8.2
The oscillator source (and operating mode) that is used
at a device Power-on Reset event is selected using Con-
figuration bit settings. The oscillator Configuration bit
settings are located in the Configuration registers in the
program memory (refer to Section 26.1 “Configuration
Bits” for further details). The Primary Oscillator
Word 2<1:0>), and the Initial Oscillator Select Configu-
ration bits, FNOSC<2:0> (Configuration Word 2<10:8>),
select the oscillator source that is used at a Power-on
Reset. The FRC Primary Oscillator with Postscaler
(FRCDIV) is the default (unprogrammed) selection. The
secondary oscillator, or one of the internal oscillators,
may be chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 8-1.
8.2.1
The
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when the
FCKSM<1:0> bits are both programmed (‘00’).
POSCMD<1:0>
FCKSM
11
xx
11
11
01
00
10
01
00
11
11
Initial Configuration on POR
CLOCK SWITCHING MODE
CONFIGURATION BITS
bits,
Configuration
POSCMD<1:0>
 2010 Microchip Technology Inc.
FNOSC<2:0>
111
110
101
100
011
011
010
010
010
001
000
bits
(Configuration
(Configuration
Notes
1, 2
1
1
1
1
1

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