PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 113

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.4.2
At a minimum, performing a clock switch requires this
basic sequence:
1.
2.
3.
4.
5.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
2.
3.
4.
5.
6.
 2010 Microchip Technology Inc.
Note 1: The processor will continue to execute
If
(OSCCON<14:12>) to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSCx bits
(OSCCON<10:8>) for the new oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit to initiate the oscillator
switch.
The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bit values are transferred to the COSCx
bits.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM is
enabled) or SOSC (if SOSCEN remains set).
2: Direct clock switches between any
desired,
OSCILLATOR SWITCHING
SEQUENCE
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
read
the
COSCx
bits
PIC24FJ64GB004 FAMILY
A recommended code sequence for a clock switch
includes the following:
1.
2.
3.
4.
5.
6.
7.
8.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 8-1.
EXAMPLE 8-1:
;Place the new oscillator selection in
W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Set new oscillator selection
MOV.b
;OSCCONL (low byte) unlock sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Start oscillator switch operation
BSET
Disable interrupts during the OSCCON register
unlock and write sequence.
Execute the unlock sequence for the OSCCON
high byte by writing 78h and
OSCCON<15:8>
instructions.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
Execute the unlock sequence for the OSCCON
low
OSCCON<7:0> in two back-to-back instructions.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Continue to execute code that is not
clock-sensitive (optional).
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
failure.
byte
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
w3, [w1]
WREG, OSCCONH
#OSCCONL, w1
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
OSCCON,#0
by
writing
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
in
46h
two
DS39940D-page 113
and
back-to-back
9Ah to
57h
to