PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 119

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.4.2
When entering Deep Sleep mode, there are certain
circumstances that require a delay between setting the
DSEN bit and executing the PWRSAV instruction. These
can be generally reduced to three scenarios:
1.
2.
3.
In the first scenario, the application requires a wake-up
from Deep Sleep on the assertion of the INT0 pin or the
RTCC interrupt. In this case, three NOP instructions
must be inserted to properly synchronize the detection
of an asynchronous INT0 interrupt after the device
enters Deep Sleep mode. If the application does not
use wake-up on INT0 or RTCC, the NOP instructions
are optional.
In the second scenario, the application also uses
interrupts which can be briefly ignored. With these
applications, an interrupt event during the execution of
the NOP instructions may cause an ISR to be executed.
This means that more than three instruction cycles will
elapse before returning to the code and that the DSEN
bit will be cleared. To prevent the missed entry into
Deep Sleep, temporarily disable interrupts prior to
entering Deep Sleep mode. Invoking the DISI instruc-
tion for four cycles is sufficient to prevent interrupts
from disrupting Deep Sleep entry.
In the third scenario, interrupts cannot be ignored even
briefly; constant interrupt detection is required, even
during the interval between setting DSEN and executing
the PWRSAV instruction. For these cases, it is possible to
disable interrupts and test for an interrupt condition,
skipping the PWRSAV instruction if necessary. Testing for
interrupts can be accomplished by checking the status of
the CPUIRQ bit (INTTREG<15>); if an unserviced inter-
rupt is pending, this bit will be set. If CPUIRQ is set prior
to executing the PWRSAV instruction, the instruction is
skipped. At this point, the DISI instruction has expired
(being more than 4 instructions from when it was
executed) and the application vectors to the appropriate
ISR. When the application returns, it can either attempt
to re-enter Deep Sleep mode or perform some other
system function. In either case, the application must
have some functional code located, following the
PWRSAV instruction, in the event that the PWRSAV
instruction is skipped and the device does not enter
Deep Sleep mode.
 2010 Microchip Technology Inc.
Scenario (1): use an external wake-up source
(INT0) or the RTCC
Scenario (2): with application-level interrupts
that can be temporarily disabled
Scenario (3): with interrupts that must be
monitored
Special Cases when Entering Deep
Sleep Mode
PIC24FJ64GB004 FAMILY
Examples for implementing these cases are shown in
Example 9-2. It is recommended that an assembler, or
in-line C routine, be used in these cases to ensure that
the code executes in the number of cycles required.
EXAMPLE 9-2:
// Case 1: simplest delay scenario
//
asm("bset
asm("nop");
asm("nop");
asm("nop");
asm("pwrsav #0");
//
// Case 2: interrupts disabled
//
asm("disi #4");
asm("bset
asm("nop");
asm("nop");
asm("nop");
asm("pwrsav #0");
//
// Case 3: interrupts disabled with
// interrupt testing
//
asm("disi #4");
asm("bset
asm("nop");
asm("nop");
asm("btss
asm("pwrsav #0");
// continue with application code here
//
DSCON, #15");
DSCON, #15");
DSCON, #15");
INTTREG, #15");
IMPLEMENTING THE
SPECIAL CASES FOR
ENTERING DEEP SLEEP
DS39940D-page 119