PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 120

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Price
Part Number:
PIC24FJ64GB002-I/SS
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Part Number:
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PIC24FJ64GB004 FAMILY
9.2.4.3
Deep Sleep mode exits on any one of the following events:
• POR event on V
• DSWDT time-out. When the DSWDT timer times
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
Exiting Deep Sleep mode generally does not retain the
state of the device and is equivalent to a Power-on
Reset (POR) of the device. Exceptions to this include
the RTCC (if present), which remains operational
through the wake-up, the DSGPRx registers and
DSWDT.
Wake-up events that occur from the time Deep Sleep
exits, until the time that the POR sequence completes,
are ignored and are not captured in the DSWAKE
register.
The sequence for exiting Deep Sleep mode is:
1.
2.
3.
4.
5.
6.
DS39940D-page 120
circuit to re-arm the V
external V
natural arming voltage of the POR circuit.
out, the device exits Deep Sleep.
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note:
After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON<10>).
This bit will be set if there was an exit from Deep
Sleep mode. If the bit is set, clear it.
Determine the wake-up source by reading the
DSWAKE register.
Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON<1>).
If application context data has been saved, read
it back from the DSGPR0 and DSGPR1
registers.
Clear the RELEASE bit (DSCON<0>).
Any interrupt pending when entering Deep
Sleep mode is cleared.
DD
Exiting Deep Sleep Mode
supply must be lowered to the
DD
supply. If there is no DSBOR
DD
supply POR circuit, the
significantly faster if V
9.2.4.4
Since wake-up from Deep Sleep results in a POR, the
wake-up time from Deep Sleep is the same as the
device POR time. Also, because the internal regulator
is turned off, the voltage on V
on how long the device is asleep. If V
below 2V, then there will be additional wake-up time
while the regulator charges V
Deep Sleep wake-up time is specified in Section 29.0
“Electrical Characteristics” as T
tion indicates the worst case wake-up time, including the
full POR Reset time (including T
as the time to fully charge a 10 F capacitor on V
which has discharged to 0V. Wake-up may be
9.2.4.5
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because V
supplied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
Purpose registers, DSGPR0 and DSGPR1, or data
EEPROM (if available). Unlike other SFRs, the con-
tents of these registers are preserved while the device
is in Deep Sleep mode. After exiting Deep Sleep,
software can restore the data by reading the registers
and clearing the RELEASE bit (DSCON<0>).
9.2.4.6
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRIS bit set) prior to entry into
Deep Sleep remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRIS bit
clear) prior to entry into Deep Sleep remain as output
pins during Deep Sleep. While in this mode, they
continue to drive the output level determined by their
corresponding LAT bit at the time of entry into Deep
Sleep.
Deep Sleep Wake-up Time
Saving Context Data with the
DSGPR0/DSGPR1 Registers
I/O Pins During Deep Sleep Mode
CAP
 2010 Microchip Technology Inc.
has not discharged.
CAP
CAP
POR
DDCORE
.
DSWU
may drop depending
and T
CAP
. This specifica-
power is not
has dropped
RST
), as well
CAP

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