PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 123

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC24FJ64GB002-I/SS
0
REGISTER 9-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0, HC
DSEN
U-0
2:
3:
(1)
These bits are reset only in the case of a POR event outside of Deep Sleep mode.
Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.
This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.
DSEN: Deep Sleep Enable bit
1 = Device entered Deep Sleep when PWRSAV #0 was executed in the next instruction
0 = Device entered normal Sleep when PWRSAV #0 was executed
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event Status bit
1 = The DSBOR is active and a BOR event is detected during Deep Sleep
0 = The DSBOR is disabled or is active and does not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Deep Sleep Release bit
1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT
0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the
and TRIS configuration
LAT and TRIS configurations, and the SOSCEN bit.
U-0
U-0
DSCON: DEEP SLEEP CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U-0
U-0
(1)
PIC24FJ64GB004 FAMILY
U-0
U-0
(1,2,3)
C = Clearable bit
‘0’ = Bit is cleared
HCS = Hardware Clearable/Settable bit
U-0
U-0
(1,2)
U-0
U-0
U = Unimplemented, read as ‘0’
x = Bit is unknown
DSBOR
R/W-0, HCS
U-0
(1,2,3)
DS39940D-page 123
RELEASE
R/C-0, HS
U-0
(1,2)
bit 8
bit 0

Related parts for PIC24FJ64GB002-I/SS