PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 183

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.2
To compute the Baud Rate Generator (BRG) reload
value, use Equation 16-1.
EQUATION 16-1:
TABLE 16-1:
TABLE 16-2:
 2010 Microchip Technology Inc.
Note 1:
Note 1:
Required System F
Note 1: Based on F
Slave Address
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
2:
2:
3:
2: These clock rate values are for guidance
I2CxBRG
Setting Baud Rate When
Operating as a Bus Master
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
F
1 MHz
1 MHz
1 MHz
SCL
PLL are disabled.
only. The actual clock rate can be affected
by various system level parameters. The
actual clock rate should be measured in
its intended application.
or
Based on F
These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
The address bits listed here will never cause an address match, independent of address mask settings.
The address will be Acknowledged only if GCEN = 1.
A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
=
--------------------------------------------------------------------- -
I2CxBRG
I
I
2
2
=
C™ CLOCK RATES
C™ RESERVED ADDRESSES
R/W Bit


SCL
COMPUTING BAUD RATE
RELOAD VALUE
----------- -
F
CY
F
CY
SCL
0
1
x
x
x
x
x
x
CY
= F
= F
+ +
–
F
1
----------------------------- -
10 000 000
OSC
OSC
CY
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte

16 MHz
16 MHz
16 MHz
----------------------------- -
10 000 000
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
F
/2, Doze mode and
/2, Doze mode and PLL are disabled.
CY
F

CY

F
CY



(1,2)
–
(1,2)
1
PIC24FJ64GB004 FAMILY
(Decimal)
(2)
157
78
39
37
18
13
(1)
(3)
9
4
6
3
I2CxBRG Value
16.3
The I2CxMSK register (Register 16-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses: ‘0000000’ and ‘0100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Note:
Description
(Hexadecimal)
Slave Address Masking
9D
4E
27
25
12
As a result of changes in the I
col, the addresses in Table 16-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
D
9
4
6
3
Actual F
1.026 MHz
1.026 MHz
0.909 MHz
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
99 kHz
DS39940D-page 183
SCL
2
C™ proto-