PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 209

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC24FJ64GB002-I/SS
0
18.5.2
1.
2.
3.
4.
5.
6.
7.
 2010 Microchip Technology Inc.
Follow
Section 18.5.1 “Enable Host Mode and Dis-
cover a Connected Device” to discover a
device.
Set up the Endpoint Control register for
bidirectional control transfers by writing 0Dh to
U1EP0 (this sets the EPCONDIS, EPTXEN, and
EPHSHK bits).
Place a copy of the device framework setup
command in a memory buffer. See Chapter 9 of
the USB 2.0 specification for information on the
device framework command set.
Initialize the buffer descriptor (BD) for the
current (EVEN or ODD) Tx EP0, to transfer the
eight bytes of command data for a device
framework command (i.e., a GET DEVICE
DESCRIPTOR):
a)
b)
Set the USB device address of the target device
in the address register (U1ADDR<6:0>). After a
USB bus Reset, the device USB address will be
zero. After enumeration, it will be set to another
value between 1 and 127.
Write D0h to U1TOK; this is a SETUP token to
Endpoint 0, the target device’s default control
pipe. This initiates a SETUP token on the bus, fol-
lowed by a data packet. The device handshake is
returned in the PID field of BD0STAT after the
packets are complete. When the USB module
updates BD0STAT, a transfer done interrupt is
asserted (the TRNIF flag is set). This completes
the setup phase of the setup transaction as
referenced in Chapter 9 of the USB specification.
To initiate the data phase of the setup transac-
tion (i.e., get the data for the GET DEVICE
DESCRIPTOR command), set up a buffer in
memory to store the received data.
Set the BD data buffer address (BD0ADR)
to the starting address of the 8-byte
memory buffer containing the command.
Write 8008h to BD0STAT (this sets the
UOWN bit, and sets a byte count of 8).
COMPLETE A CONTROL
TRANSACTION TO A CONNECTED
DEVICE
the
procedure
described
PIC24FJ64GB004 FAMILY
in
8.
9.
10. To initiate the status phase of the setup transac-
11. Initialize the current (even or odd) Tx EP0 BD to
12. Write the Token register with the appropriate IN or
Note:
Initialize the current (EVEN or ODD) Rx or Tx
(Rx for IN, Tx for OUT) EP0 BD to transfer the
data:
a)
b)
Write the token register with the appropriate IN
or OUT token to Endpoint 0, the target device’s
default control pipe (e.g., write 90h to U1TOK for
an IN token for a GET DEVICE DESCRIPTOR
command). This initiates an IN token on the bus
followed by a data packet from the device to the
host. When the data packet completes, the
BD0STAT is written and a transfer done interrupt
is asserted (the TRNIF flag is set). For control
transfers with a single packet data phase, this
completes the data phase of the setup transac-
tion as referenced in Chapter 9 of the USB
specification. If more data needs to be
transferred, return to step 8.
tion, set up a buffer in memory to receive or send
the zero length status phase data packet.
transfer the status data:
a)
b)
OUT token to Endpoint 0, the target device’s
default control pipe (e.g., write 01h to U1TOK for
an OUT token for a GET DEVICE DESCRIPTOR
command). This initiates an OUT token on the
bus followed by a zero length data packet from
the host to the device. When the data packet
completes, the BD is updated with the handshake
from the device, and a transfer done interrupt is
asserted (the TRNIF flag is set). This completes
the status phase of the setup transaction as
described in Chapter 9 of the USB specification.
Write C040h to BD0STAT. This sets the
UOWN, configures Data Toggle (DTS) to
DATA1, and sets the byte count to the
length of the data buffer (64 or 40h, in this
case).
Set BD0ADR to the starting address of the
data buffer.
Set the BDT buffer address field to the start
address of the data buffer
Write 8000h to BD0STAT (set UOWN bit,
configure DTS to DATA0, and set byte
count to 0).
Only one control transaction can be
performed per frame.
DS39940D-page 209

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