PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 222

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC24FJ64GB002-I/SS
0
PIC24FJ64GB004 FAMILY
18.7.2
REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY)
DS39940D-page 222
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/K-0, HS
Note:
IDIF
U-0
V
USB INTERRUPT REGISTERS
Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
BUS
Unimplemented: Read as ‘0’
IDIF: ID State Change Indicator bit
1 = Change in ID state is detected
0 = No ID state change
T1MSECIF: 1 Millisecond Timer bit
1 = The 1 millisecond timer has expired
0 = The 1 millisecond timer has not expired
LSTATEIF: Line State Stable Indicator bit
1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different
0 = USB line state has not been stable for 1 ms
ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+/D- lines or V
0 = No activity on the D+/D- lines or V
SESVDIF: Session Valid Change Indicator bit
1 = V
0 = V
SESENDIF: B-Device V
1 = V
0 = V
Unimplemented: Read as ‘0’
VBUSVDIF A-Device V
1 = V
0 = No V
T1MSECIF
R/K-0, HS
threshold crossings may be either rising or falling.
from last time
OTG Specification)
OTG Specification)
U-0
BUS
BUS
BUS
BUS
BUS
BUS
has crossed V
has not crossed V
has not crossed V
change on B-device is detected; V
change on A-device is detected; V
change on A-device is detected
K = Write ‘1’ to clear bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
LSTATEIF
R/K-0, HS
U-0
BUS
(1)
(1)
BUS
A
_
SESS
Change Indicator bit
A
Change Indicator bit
A
_
_
SESS
SESS
R/K-0, HS
_
ACTVIF
END
U-0
BUS
_
_
END
END
(as defined in the USB OTG Specification)
BUS
is detected
is detected
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/K-0, HS
BUS
SESVDIF
BUS
U-0
has crossed V
has crossed V
SESENDIF
R/K-0, HS
U-0
B
A
_
_
SESS
VBUS
 2010 Microchip Technology Inc.
_
_
x = Bit is unknown
END
VLD
(as defined in the USB
(as defined in the USB
U-0
U-0
(1)
VBUSVDIF
R/K-0, HS
U-0
bit 8
bit 0

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