PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 253

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.0
FIGURE 21-1:
FIGURE 21-2:
 2010 Microchip Technology Inc.
Note:
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
Shift Buffer
Data
32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
2: Polynomial length n is determined by ([PLEN<3:0>] + 1).
2 * F
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Section
Cyclic
(DS39729).
CY
Shift Clock
Redundancy
41.
Family
CRC BLOCK DIAGRAM
CRC SHIFT ENGINE DETAIL
“32-Bit
Bit 0
Reference
Read/Write Bus
Check
CRCWDATH
Programmable
CRCDATH
(4x32, 8x16 or 16x8)
CRC Shift Engine
X(1)
Manual”,
Variable FIFO
(CRC)”
Shift Buffer
(1)
CRCWDATH
0
PIC24FJ64GB004 FAMILY
1
Bit 1
CRCWDATL
CRCDATL
LENDIAN
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable Interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in Figure 21-1. A simple version of the CRC shift
engine is shown in Figure 21-2.
up to 32 bits
X(2)
Shift Complete Event
FIFO Empty Event
(1)
Bit 2
CRCWDATL
CRCISEL
1
0
X(n)
Set CRCIF
(1)
DS39940D-page 253
Bit n
(2)