PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 269

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.0
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be con-
figured to use any one of four external analog inputs, as
well as voltage reference inputs from the voltage
reference generator and band gap reference.
FIGURE 23-1:
 2010 Microchip Technology Inc.
Note:
C
C
C
CV
C
CV
CCH<1:0>
CREF
X
X
X
X
INB
INC
IND
INA
TRIPLE COMPARATOR
MODULE
REF
REF
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual”,
Comparator Module” (DS39734).
-
+
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
Section
Select
Logic
Input
46.
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
-
+
-
+
-
+
“Scalable
C1
C2
C3
PIC24FJ64GB004 FAMILY
CPOL
EVPOL<1:0>
EVPOL<1:0>
EVPOL<1:0>
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 23-1. Diagrams of the possible individual
comparator configurations are shown in Figure 23-2.
Each comparator has its own control register,
CMxCON (Register 23-1), for enabling and configuring
its operation. The output and event status of all three
comparators are provided in the CMSTAT register
(Register 23-2).
Trigger/Interrupt
Trigger/Interrupt
Trigger/Interrupt
Logic
Logic
Logic
COE
COE
COE
CEVT
CEVT
COUT
CEVT
COUT
COUT
DS39940D-page 269
C1OUT
C2OUT
C3OUT
Pin
Pin
Pin