PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 289

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.3.1
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
is executed before that window causes a WDT Reset;
this is similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<6>) to ‘0’.
FIGURE 26-2:
26.4
PIC24FJ64GB004 family devices have both a WDT
module and a DSWDT module. The latter runs, if
enabled, when a device is in Deep Sleep and is driven
by either the SOSC or LPRC Oscillator. The clock
source is selected by the DSWDTOSC (CW4<4>)
Configuration bit.
The DSWDT can be configured to generate a time-out
at 2.1 ms to 25.7 days by selecting the respective
postscaler. The postscaler can be selected by the
Configuration bits, DSWDTPS<3:0> (CW4<3:0>).
When the DSWDT is enabled, the clock source is also
enabled. DSWDT is one of the sources that can wake
the device from Deep Sleep mode.
 2010 Microchip Technology Inc.
Sleep or Idle Mode
New Clock Source
All Device Resets
CLRWDT Instr.
PWRSAV Instr.
Exit Sleep or
Transition to
LPRC Input
Deep Sleep Watchdog Timer
(DSWDT)
Idle Mode
SWDTEN
FWDTEN
WINDOWED OPERATION
WDT BLOCK DIAGRAM
31 kHz
(5-bit/7-bit)
Prescaler
FWPSA
1 ms/4 ms
LPRC Control
PIC24FJ64GB004 FAMILY
Counter
WDT
26.3.2
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The WDT
software option allows the user to enable the WDT for
critical code segments, and disable the WDT during
non-critical segments, for maximum power savings.
26.5
PIC24FJ64GB004 family devices provide two compli-
mentary methods to protect application code from
overwrites and erasures. These also help to protect the
device from inadvertent configuration changes during
run time.
26.5.1
For all devices in the PIC24FJ64GB004 family, the
on-chip program memory space is treated as a single
block, known as the General Segment (GS). Code pro-
tection for this block is controlled by one Configuration
bit, GCP. This bit inhibits external reads and writes to
the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
1:1 to 1:32.768
WDTPS<3:0>
Postscaler
Program Verification and
Code Protection
CONTROL REGISTER
GENERAL SEGMENT PROTECTION
DS39940D-page 289
WDT Overflow
Wake From Sleep
Reset