PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 290

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
26.5.2
In addition to global General Segment protection, a
separate subrange of the program memory space can
be individually protected against writes and erases.
This area can be used for many purposes where a sep-
arate block of erase and write-protected code is
needed, such as bootloader applications. Unlike
common boot block implementations, the specially
protected segment in the PIC24FJ64GB004 family
devices can be located by the user anywhere in the
program space and configured in a wide range of sizes.
Code segment protection provides an added level of
protection to a designated area of program memory, by
disabling the NVM safety interlock, whenever a write or
erase address falls within a specified range. It does not
override General Segment protection controlled by the
GCP or GWRP bits. For example, if GCP and GWRP
are enabled, enabling segmented code protection for
the bottom half of program memory does not undo
General Segment protection for the top half.
The size and type of protection for the segmented code
range are configured by the WPFPx, WPEND, WPCFG
and WPDIS bits in Configuration Word 3. Code seg-
ment protection is enabled by programming the WPDIS
bit (= 0). The WPFP bits specify the size of the segment
to be protected by specifying the 512-word code page
that is the start or end of the protected segment. The
specified region is inclusive, therefore, this page will
also be protected.
The WPEND bit determines if the protected segment
uses the top or bottom of the program space as a
boundary. Programming WPEND (= 0) sets the bottom
of program memory (000000h) as the lower boundary
of the protected segment. Leaving WPEND unpro-
grammed (= 1) protects the specified page through the
last page of implemented program memory, including
the Configuration Word locations.
TABLE 26-2:
DS39940D-page 290
WPDIS
Segment Configuration Bits
1
1
0
0
0
0
CODE SEGMENT PROTECTION
WPEND
x
x
1
0
1
0
SEGMENT CODE PROTECTION CONFIGURATION OPTIONS
WPCFG
1
0
0
0
1
1
No additional protection enabled; all program memory protection is configured
by GCP and GWRP
Last code page protected, including Flash Configuration Words
Addresses from the first address of code page, defined by WPFP<5:0> through
the end of implemented program memory (inclusive), are protected, including
Flash Configuration Words
Address, 000000h, through the last address of code page, defined by
WPFP<5:0> (inclusive) is protected
Addresses from first address of code page, defined by WPFP<5:0> through the
end of implemented program memory (inclusive), are protected, including Flash
Configuration Words
Addresses from first address of code page, defined by WPFP<5:0> through the
end of implemented program memory (inclusive), are protected
Write/Erase Protection of Code Segment
memory, as well as the Flash Configuration Words.
A separate bit, WPCFG, is used to independently protect
the last page of program space, including the Flash Con-
figuration Words. Programming WPCFG (= 0) protects
the last page, regardless of the other bit settings. This
may be useful in circumstances where write protection is
needed for both a code segment in the bottom of
The various options for segment code protection are
shown in Table 26-2.
26.5.3
The Configuration registers are protected against
inadvertent or unwanted changes, or reads in two
ways. The primary protection method is the same as
that of the RP registers – shadow registers contain a
complimentary value which is constantly compared
with the actual value.
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence. Even
if General Segment protection is not enabled, the
device configuration can be protected by using the
appropriate code cement protection setting.
CONFIGURATION REGISTER
PROTECTION
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