PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 31

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.
4.1
The
PIC24FJ64GB004 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 4-1:
 2010 Microchip Technology Inc.
Note:
program
MEMORY ORGANIZATION
Program Address Space
Memory areas are not shown to scale.
address
PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GB004 FAMILY DEVICES
Device Config Registers
memory
PIC24FJ32GB00X
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
Program Memory
(11K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
space
of
PIC24FJ64GB004 FAMILY
the
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ64GB004 family of
devices are shown in Figure 4-1.
Device Config Registers
Alternate Vector Table
PIC24FJ64GB00X
Interrupt Vector Table
Flash Config Words
Program Memory
(22K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
0057FEh
005800h
00ABFEh
00AC00h
7FFFFFh
800000h
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
FFFFFFh
DS39940D-page 31