PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 48

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-24:
TABLE 4-25:
TABLE 4-26:
DSCON
DSWAKE
DSGPR0
DSGPR1
Legend:
Note 1:
RCON
OSCCON
CLKDIV
OSCTUN
REFOCON
Legend:
Note 1:
NVMCON
NVMKEY
Legend:
Note 1:
File Name
File Name
File Name
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Deep Sleep registers are only reset on a V
Addr
0760
0766
Addr
075A
075C
075E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Reset value of the RCON register is dependent on the type of Reset event. See Section 6.0 “Resets” for more information.
The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 8.0 “Oscillator Configuration” for more information.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
Addr
0740
074E
758
0742
0744
0748
SYSTEM REGISTER MAP
DEEP SLEEP REGISTER MAP
NVM REGISTER MAP
DSEN
Bit 15
Bit 15
TRAPR
ROEN
Bit 15
WR
—
—
ROI
—
—
IOPUWR
Bit 14
WREN
COSC2
Bit 14
DOZE2
Bit 14
—
—
—
—
—
Bit 13
WRERR
ROSSLP
Bit 13
COSC1
DOZE1
—
—
Bit 13
—
—
—
Bit 12
COSC0
DOZE0
ROSEL
Bit 12
Bit 12
—
—
—
—
—
—
DD
POR event.
Bit 11
RODIV3
DOZEN
Bit 11
—
—
Bit 11
—
—
—
—
—
Bit 10
RCDIV2
RODIV2
NOSC2
DPSLP
Bit 10
—
—
Bit 10
—
—
—
Bit 9
RCDIV1
RODIV1
Deep Sleep General Purpose Register 0
Deep Sleep General Purpose Register 1
NOSC1
—
—
Bit 9
Bit 9
CM
—
—
—
DSINT0
Bit 8
RCDIV0
RODIV0
PMSLP
NOSC0
—
Bit 8
Bit 8
—
—
—
DSFLT
CLKLOCK
Bit 7
CPDIV1
Bit 7
—
EXTR
Bit 7
—
—
—
ERASE
Bit 6
IOLOCK
CPDIV0
Bit 6
—
—
SWR
Bit 6
—
—
SWDTEN
Bit 5
Bit 5
PLLEN
LOCK
—
—
TUN5
Bit 5
—
—
NVMKEY Register<7:0>
DSWDT
Bit 4
Bit 4
WDTO
—
TUN4
Bit 4
—
—
—
—
DSRTC
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
Bit 3
SLEEP
Bit 3
—
TUN3
Bit 3
CF
—
—
DSMCLR
POSCEN SOSCEN OSWEN
Bit 2
Bit 2
TUN2
—
Bit 2
IDLE
—
—
DSBOR RELEASE
Bit 1
Bit 1
—
TUN1
Bit 1
BOR
—
—
DSPOR
Bit 0
Bit 0
TUN0
Bit 0
POR
—
—
Resets
Resets
0000
0000
0001
0000
0000
Resets
Note 1
Note 2
0100
0000
0000
All
All
All
(1)
(1)