16 Bit MCU 40MIPS 64 KB FLASH 28 QFN-S 6x6mm T/R

PIC24HJ64GP502T-I/MM

Manufacturer Part NumberPIC24HJ64GP502T-I/MM
Description16 Bit MCU 40MIPS 64 KB FLASH 28 QFN-S 6x6mm T/R
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP502T-I/MM datasheets
 

Specifications of PIC24HJ64GP502T-I/MM

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o21
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 10x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-QFN
Processor SeriesPIC24HJCorePIC
Data Bus Width16 bitData Ram Size8 KB
Interface TypeI2C, SPI, UARTMaximum Clock Frequency40 MHz
Number Of Programmable I/os21Number Of Timers5
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature- 40 COn-chip Adc10 bit, 10 Channel / 12 bit, 10 Channel
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithAC164336 - MODULE SOCKET FOR PM3 28/44QFN
Eeprom Size-  
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5.4
Flash Memory Programming in
ICSP Mode
5.4.1
PROGRAMMING OPERATIONS
Flash memory write and erase operations are
controlled by the NVMCON register. Programming is
performed by setting NVMCON to select the type of
erase
operation
(Table
5-2)
or
(Table
5-3) and initiating the programming by setting
the WR control bit (NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing of
the WR control bit when the programming operation is
complete. Please refer to
Section 8.0 “AC/DC
Characteristics and Timing Requirements”
detailed information about the delays associated with
various programming operations.
TABLE 5-2:
NVMCON ERASE OPERATIONS
NVMCON
Erase Operation
Value
Erase all code memory, executive
0x404F
memory and CodeGuard™ Configuration
registers (does not erase Unit ID or
Device ID registers).
Erase General Segment and FGS
0x404D
Configuration register.
Erase Secure Segment and FSS
0x404C
Configuration register. This operation will
also erase the General Segment and
FGS Configuration register.
0x4042
Erase a page of code memory or
executive memory.
FIGURE 5-5:
ENTERING ICSP™ MODE
P6
P21
P14
MCLR
V
DD
PGDx
PGCx
P18
© 2010 Microchip Technology Inc.
TABLE 5-3:
NVMCON
Value
0x4001
0x4000
write
operation
0x4003
5.4.2
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Setting the WR bit initiates the
programming cycle.
All erase and write cycles are self-timed. The WR bit
for
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
BSET
V
IH
Program/Verify Entry Code = 0x4D434851
0
1
0
0
1
0
...
b31
b30
b29
b28
b27
b3
P1A
P1B
NVMCON WRITE OPERATIONS
Write Operation
Program 1 row (64 instruction words)
of code memory or executive memory.
Write a Configuration register byte.
Program a code memory word.
STARTING AND STOPPING A
PROGRAMMING CYCLE
NVMCON, #WR
P19
P7
V
IH
0
0
1
b2
b1
b0
DS70152H-page 35