16 Bit MCU 40MIPS 64 KB FLASH 28 QFN-S 6x6mm T/R

PIC24HJ64GP502T-I/MM

Manufacturer Part NumberPIC24HJ64GP502T-I/MM
Description16 Bit MCU 40MIPS 64 KB FLASH 28 QFN-S 6x6mm T/R
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP502T-I/MM datasheets
 

Specifications of PIC24HJ64GP502T-I/MM

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o21
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 10x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-QFN
Processor SeriesPIC24HJCorePIC
Data Bus Width16 bitData Ram Size8 KB
Interface TypeI2C, SPI, UARTMaximum Clock Frequency40 MHz
Number Of Programmable I/os21Number Of Timers5
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature- 40 COn-chip Adc10 bit, 10 Channel / 12 bit, 10 Channel
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithAC164336 - MODULE SOCKET FOR PM3 28/44QFN
Eeprom Size-  
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Revision H (October 2010)
This revision includes the following updates:
• Text and formatting updates have been
incorporated throughout the document
• All references to V
/V
have been
CAP
DDCORE
changed to: V
CAP
• All occurrences of PGC and PGD have been
changed to PGCx and PGDx, respectively
• Added topics covered in
Section 1.0 “Device
Overview”
• Moved the Checksum Computation table to the
appendix (see
Table
D-1)
• Updated all occurrences of TBLPG to TBLPAG
throughout the document
• Removed the ERASEB command from the
Command Set Summary (see
Table
• Updated the High-Level Enhanced ICSP™
Programming Flow (see
Figure
3-1)
• Replaced the Device Configuration Register Map
(previously Table 4-3) with individual tables for
each dsPIC33F/PIC24H device family (see
Table 3-3
through
Table
3-12)
• Updated the Note in
Section 3.6.2
“Programming Methodology”
• Changed Opcode 0x7 to Reserved in the
Programming Executive Command Set (see
Table
4-1)
• Removed 4.2.10 “ERASEB Command”
• Updated the table cross-references in
Section 5.7 “Writing Configuration Memory”
• Combined all Default Configuration Register
Values tables into one table (see
Table
• Relocated the paragraph on ICSP programming
details, which now appears just before
• Added a Note to
Section 6.1 “Overview”
• Updated Step 4 in Programming the Programming
Executive (see
Table
6-1)
• Updated Device IDs and Revision IDs (see
Table
7-1)
• Updated parameters D111, P1, P1A and P1B in
the AC/DC Characteristics and Timing
Requirements (see
Table
8-1)
• Added Checksum Computation Example When
Using CodeGuard™ Security (see
Table
DS70152H-page 82
3-1)
5-6)
Table 5-7
D-2).
© 2010 Microchip Technology Inc.