PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 78

• Manufacturer Part Number: PIC24HJ64GP510A-E/PF
• Description: 16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-1:
REGISTER 7-2:
DS70592B-page 78
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
Note 1: For complete register details, see Register 3-1.
Note 1: For complete register details, see Register 3-2.
R/W-0
IPL2
U-0
U-0
U-0
—
—
—
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
(2)
(3)
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
R/W-0
IPL1
U-0
U-0
U-0
—
—
—
SR: CPU STATUS REGISTER
CORCON: CORE CONTROL REGISTER
(2)
(3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/W-0
IPL0
U-0
U-0
U-0
—
—
—
(2)
(3)
U-0
R-0
U-0
U-0
RA
Preliminary
—
—
—
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
-n = Value at POR
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/C-0
U-0
U-0
—
—
N
(2)
(2)
(1)
R/W-0
R/W-0
PSV
U-0
U-0
OV
—
—
 2009 Microchip Technology Inc.
‘1’ = Bit is set
R/W-0
U-0
U-0
U-0
—
—
—
Z
R/W-0
R/W-0
U-0
U-0
DC
—
—
C
bit 8
bit 0
bit 8
bit 0