PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 2

• Manufacturer Part Number: PIC24HJ64GP510A-E/PF
• Description: 16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
DS80468D-page 2
Note 1:
Operations
Regulator
Module
Internal
Voltage
ECAN
ECAN
UART
UART
UART
UART
I
CPU
ADC
PSV
2
SPI
SPI
I
I
I
I/O
All
C™
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Transmission
Consumption
Frame Mode
Sleep Mode
High-Speed
Addressing
Addressing
Addressing
Generation
Instruction
Operation
Character
SDO1 Pin
Operation
Interrupts
Transmit
SILICON ISSUE SUMMARY
IR Mode
Queuing
Feature
in Sleep
Current
150ºC
Mode
10-bit
Mode
10-bit
Mode
10-bit
Mode
Break
Mode
EXCH
I
—
—
PD
Number
Item
10.
12.
13.
14.
15.
16.
17.
18.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device is interrupted from Sleep
due to activity on the CAN bus.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and using two Stop
bits (STSEL = 1), it may sample the first Stop bit instead of the
second one.
The UART error interrupt may not occur, or may occur at an
incorrect time, if multiple errors occur during a short period of
time.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
After the ACKSTAT bit is set when receiving a NACK, it may
be cleared by the reception of a Start or Stop bit.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit reserved
addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
In framed SPI mode, when the FRMDLY bit (SPIxCON2<1>) is
cleared and SMP bit (SPIxCON1<9>) is cleared, frame sync
pulses do not get generated.
When the VREGS bit (RCON<8>) is set to a logic ‘0’, device
may Reset and higher sleep current may be observed.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The EXCH instruction does not execute correctly.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause SPI module to ignore written data.
ECAN module may not transmit Buffer 0 data if Buffer 1 data is
queued for transmission first.
The UART module will not generate back-to-back Break
characters.
SDO1 pin may toggle while device is being programmed via
PGECx/PGEDx pin pairs.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
may exceed the device data sheet specifications.
These revisions of silicon only support 140ºC operation
instead of 150ºC for Hi-Temp operating temperature.
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
Issue Summary
PD
2
C devices, the
© 2010 Microchip Technology Inc.
) of the device
Revisions
A3
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)