PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 3

• Manufacturer Part Number: PIC24HJ64GP510A-E/PF
• Description: 16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: ECAN
2. Module: UART
© 2010 Microchip Technology Inc.
Note:
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN Event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Affected Silicon Revisions
A3
A3
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A4
A4
X
X
repetitive
Interrupt
Service
Routine
3. Module: UART
4. Module: UART
5. Module: I
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are
configured for 10-bit addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
Affected Silicon Revisions
A3
A3
A3
X
X
X
2
C devices, the addresses as well as bits
A4
A4
A4
X
X
X
2
C
2
C devices on the bus, one of
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