16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part NumberPIC24HJ64GP510A-E/PF
Description16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP510A-E/PF datasheets
 

Specifications of PIC24HJ64GP510A-E/PF

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o85
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 32x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Page 33/84

Download datasheet (2Mb)Embed
PrevNext
5.2
Entering ICSP Mode
As illustrated in
Figure
5-5, entering ICSP Program/
Verify mode requires three steps:
1.
MCLR is briefly driven high then low (P21)
2.
A 32-bit key sequence is clocked into PGDx.
3.
MCLR is then driven high within a specified
period of time and held.
Note 1: The MCLR capacitor value can vary the
high time required for entering ICSP
mode.
The programming voltage applied to MCLR is V
which is essentially V
in the case of dsPIC33F/
DD
PIC24H devices. There is no minimum time require-
ment for holding at V
. After V
is removed, an interval
IH
IH
of at least P18 must elapse before presenting the key
sequence on PGDx.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more
easily
remembered
as
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit of the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P19 and P7 must elapse before presenting
data on PGDx. Signals appearing on PGDx before P7
has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
5.3
ICSP Operation
After entering into ICSP mode, the CPU is Idle.
Execution of the CPU is governed by an internal state
machine. A 4-bit control code is clocked in using PGCx
and PGDx and this control code is used to command the
CPU (see
Table
5-1).
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 5-1:
CPU CONTROL CODES IN
ICSP™ MODE
4-Bit
Mnemonic
Description
Control Code
0000b
SIX
Shift in 24-bit instruction
and execute.
0001b
REGOUT
Shift out the VISI
register.
0010b-1111b
N/A
Reserved.
© 2010 Microchip Technology Inc.
5.3.1
The SIX control code allows execution of dsPIC33F/
PIC24H Programming Specification assembly instruc-
(1)
.
tions. When the SIX code is received, the CPU is sus-
pended for 24 clock cycles, as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four clock cycles. While the received instruction
is executed, the state machine simultaneously shifts in
the next 4-bit command (see
Note 1: Coming out of the ICSP entry sequence,
,
IH
0x4D434851
in
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
must be
IH
5.3.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for eight cycles. After these
eight cycles, an additional 16 cycles are required to clock
the data out (see
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
Note:
SIX SERIAL INSTRUCTION
EXECUTION
Figure
5-3).
the first 4-bit control code is always
forced to SIX and a forced NOP instruction
is executed by the CPU. Five additional
PGCx clocks are needed on start-up,
thereby resulting in a 9-bit SIX command
instead of the normal 4-bit SIX command.
After the forced SIX is clocked in, ICSP
operation resumes as normal (the next
24 clock cycles load the first instruction
word to the CPU). See
Figure 5-2
details.
instructions must be followed by a NOP
instruction.
REGOUT SERIAL INSTRUCTION
EXECUTION
Figure
5-4).
The device will latch input PGDx data on
the rising edge of PGCx and will output
data on the PGDx line on the rising edge
of PGCx. For all data transmissions, the
Least Significant bit (LSb) is transmitted
first.
DS70152H-page 33
for