16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part NumberPIC24HJ64GP510A-E/PF
Description16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP510A-E/PF datasheets
 


Specifications of PIC24HJ64GP510A-E/PF

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o85
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 32x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Page 37/84

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5.5
Erasing Program Memory
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
0x404F and then executing the programming cycle. For
segment erase operations, the NVMCON value should
be modified suitably, according to
Table
Figure 5-6
illustrates the ICSP programming process
for Bulk Erasing program memory. This process
includes the ICSP command code, which must be
transmitted (for each instruction) Least Significant bit
first, using the PGCx and PGDx pins (see
Note:
Program memory must be erased before
writing any data to program memory.
FIGURE 5-6:
BULK ERASE FLOW
Start
Write 0x404F to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
End
If a Segment Erase operation is required, Step 3 must
be modified with the appropriate NVMCON value as
per
Table
5-2.
The ability to individually erase various segments is a
critical component of the CodeGuard™ Security
features on dsPIC33F/PIC24H devices. An individual
code segment may be erased without affecting other
segments. In addition, the Configuration register
corresponding to the erased code segment also gets
erased. For example, the user may want to erase the
code in the General Segment without erasing
a bootloader located in the Boot Segment.
© 2010 Microchip Technology Inc.
The Secure Segment Erase command is used to erase
the Secure Segment and the FSS Configuration
register. The General Segment Erase command is
used to erase the General Segment and the FGS
Configuration register. This command is only effective
if a Boot Segment or Secure Segment has been
enabled.
5-2.
Note 1: The
Configuration register can only be erased
using a Bulk Erase.
2: A Secure Segment Erase operation also
erases the General Segment and FGS
Figure
5-2).
Configuration register. This is true even if
Secure Segment is present on a device
but not enabled.
Before performing any segment erase operation, the
programmer must first determine if the dsPIC33F/
PIC24H device has defined a Boot Segment or Secure
Segment, and ensure that a segment does not get
overwritten by operations on any other segment.
The BSS bit field in the FBS Configuration register can
be read to determine whether a Boot Segment has
been defined. If a Boot Segment has already been
defined (and probably already been programmed), the
user must be warned about this fact. Similarly, the SSS
bit field in the FSS Configuration register can be read
to determine whether a Secure Segment has been
defined. If a Secure Segment has already been defined
(and probably already been programmed), the user
must be warned about this fact.
A Bulk Erase operation is the recommended
mechanism to allow a user to overwrite the Boot
Segment (if one chooses to do so).
In
general,
Security-related Configuration registers should be
programmed in the following order:
• FBS and Boot Segment
• FSS and Secure Segment
• FGS and General Segment
Boot
Segment
and
FBS
the
segments
and
CodeGuard
DS70152H-page 37