16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part NumberPIC24HJ64GP510A-E/PF
Description16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP510A-E/PF datasheets
 


Specifications of PIC24HJ64GP510A-E/PF

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o85
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 32x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Page 9/84

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3.2
Confirming the Presence of the
Programming Executive
Before programming, the programmer must confirm
that the programming executive is stored in executive
memory. The procedure for this task is illustrated in
Figure
3-2.
First, ICSP mode is entered. Then, the unique
Application ID Word stored in executive memory is read.
If the programming executive is resident, the correct
Application ID Word is read and programming can
resume as normal. However, if the Application ID Word is
not present, the programming executive must be
programmed to executive code memory using the
method described in
Section 6.0 “Programming the
Programming Executive to
Memory”. See
for the Application ID of each device.
Section 5.0 “Device Programming – ICSP”
the ICSP programming method.
Section 5.11 “Reading
the Application ID Word”
describes the procedure for
reading the Application ID Word in ICSP mode.
FIGURE 3-2:
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
Start
Enter ICSP™ Mode
Check the
Application ID
by reading Address
0x8007F0
Is
No
Application ID
(1)
present?
Yes
Prog. Executive must
be Programmed
Exit ICSP Mode
Enter Enhanced
ICSP Mode
Sanity Check
End
Note 1: See
TABLE 7-1: “Device IDs and Revi-
sion”
for the Application ID of each
device.
© 2010 Microchip Technology Inc.
3.3
Entering Enhanced ICSP Mode
As illustrated in
Figure
Program/Verify mode requires three steps:
1.
The MCLR pin is briefly driven high then low.
2.
A 32-bit key sequence is clocked into PGDx.
3.
MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is V
which is essentially V
devices. There is no minimum time requirement for
holding at V
. After V
IH
least P18 must elapse before presenting the key
sequence on PGDx.
The key sequence is a specific 32-bit pattern,
Table 7-1
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more
easily
remembered
describes
hexadecimal format). The device will enter Program/
Verify mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19 and P7 must elapse before
presenting data on PGDx. Signals appearing on PGDx
before P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Note:
When programming a device without
Peripheral Pin Select (PPS) and in
Enhanced ICSP mode, the SPI output pin
(SDOx) may toggle while the device is
being programmed.
3-3, entering Enhanced ICSP
,
IH
in case of dsPIC33F/PIC24H
DD
is removed, an interval of at
IH
as
0x4D434850
in
must be
IH
DS70152H-page 9