PIC24HJ64GP510A-I/PT Microchip Technology, PIC24HJ64GP510A-I/PT Datasheet - Page 38

16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 12x12x1mm TRAY

PIC24HJ64GP510A-I/PT

Manufacturer Part Number
PIC24HJ64GP510A-I/PT
Description
16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510A-I/PT

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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TABLE 5-4:
5.6
The procedure for writing code memory is similar to the
procedure for writing the Configuration registers,
except that 64 instruction words are programmed at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed.
Table 5-5
including the serial pattern with the ICSP command
code, which must be transmitted Least Significant bit
first using the PGCx and PGDx pins (see
In Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for programming of
code memory. In Step 3, the 24-bit starting destination
address for programming is loaded into the TBLPAG
register and W7 register. The upper byte of the
starting destination address is stored in TBLPAG and
the lower 16 bits of the destination address are stored
in W7.
To minimize the programming time, the same packed
instruction format that the programming executive uses
is utilized (see
instruction words are stored in working registers,
W0:W5, using the MOV instruction and the read pointer,
W6, is initialized. The contents of W0:W5 holding the
packed instruction word data are illustrated in
Figure
to copy the data from W0:W5 to the write latches of
code memory. Since code memory is programmed 64
instruction words at a time, Steps 4 and 5 are repeated
16 times to load all the write latches (Step 6).
DS70152H-page 38
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to erase all program memory.
Step 3: Initiate the erase cycle.
Step 4: Wait for Bulk Erase operation to complete and make sure WR bit is clear.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
5-7. In Step 5, eight TBLWT instructions are used
Writing Code Memory
shows the ICSP programming details,
Figure
SERIAL INSTRUCTION EXECUTION FOR BULK ERASING CODE MEMORY
040200
040200
000000
2404FA
883B0A
A8E761
000000
000000
000000
000000
(Hex)
Data
4-4). In Step 4, four packed
GOTO
GOTO
NOP
MOV
MOV
BSET
NOP
NOP
NOP
NOP
Externally time ‘P11’ msec (see
Timing
complete.
Figure
Requirements”) to allow sufficient time for the Bulk Erase operation to
0x200
#0x404F, W10
W10, NVMCON
NVMCON, #WR
0x200
5-2).
After the write latches are loaded, programming is
initiated by writing to the NVMCON register in Steps 7
and 8. In Step 9, the internal PC is reset to 0x200. This is
a precautionary measure to prevent the PC from
incrementing into unimplemented memory when large
devices are being programmed. Lastly, in Step 10,
Steps 3-9 are repeated until all of code memory is
programmed.
FIGURE 5-7:
W0
W1
W2
W3
W4
W5
Section 8.0 “AC/DC Characteristics and
Description
15
MSB1
MSB3
PACKED INSTRUCTION
WORDS IN W0:W5
© 2010 Microchip Technology Inc.
LSW0
LSW1
LSW2
LSW3
8
7
MSB0
MSB2
0

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