S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet

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S25FL032P 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be ...

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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...

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S25FL032P 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation – Full voltage range: 2.7 to 3.6V read and write operations Memory architecture – ...

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General Description The S25FL032P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device consists of 64 uniform 64 KB sectors with the two (Top or Bottom sectors further split up into thirty-two 4KB sub ...

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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Program Acceleration via W#/ACC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figures Figure 2.1 16-pin Plastic Small Outline Package (SO ...

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Tables Table 5.1 S25FL032P Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Block Diagram SRAM Logic 2. Connection Diagrams Note DNC = Do Not Connect (Reserved for future use) October 5, 2009 S25FL032P_00_05 Array - L RD DATA PATH IO Figure 2.1 ...

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Note There is an exposed central pad on the underside of the USON package. This should not be connected to any voltage or signal line on the PCB. Connecting the central pad to GND (V GND (V ) lead and ...

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Input/Output Descriptions Signal I/O SO/IO1 I/O SI/IO0 I/O SCK Input CS# Input HOLD#/IO3 I/O W#/ACC/IO2 I/O V Input CC GND Input October 5, 2009 S25FL032P_00_05 Figure 2.6 6x8 mm 24-ball ...

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Logic Symbol SI/IO0 SCK CS# W#/ACC/IO2 HOLD#/IO3 GND S25FL032P SO/IO1 S25FL032P_00_05 October 5, 2009 ...

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Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 032 P 5.1 Valid Combinations Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device. Base Ordering ...

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Spansion SPI Modes A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode 3) Input data is ...

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Device Operations All Spansion SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device that supports an inactive clock while CS# is held low. 7.1 Byte or Page Programming ...

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Status Register The Status Register contains the status and control bits that can be read or set by specific commands (see Table 9.1 on page 23). These bits configure different protection configurations and supply information of operation of the ...

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Bit Bit Name TBPROT BPNV 2 TBPARM 1 QUAD 0 FREEZE Note (Default) indicates the value of each Configuration Register bit set upon initial factory shipment. 7.9 Data Protection Modes Spansion SPI ...

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Status Register Block BP2 BP1 BP0 Status Register Block BP2 BP1 BP0 ...

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SCK HOLD# 7.11 Accelerated Programming Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V device uses the higher voltage on ...

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Sector Address Table The Sector Address tables show the size of the memory array, sectors, and pages. The device uses pages to cache the program data before the data is programmed into the memory array. Each page or byte ...

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Address Range Sector Start Address SS31 3FF000h SS30 3FE000h SS29 3FD000h SS28 3FC000h SS27 3FB000h SS26 3FA000h SS25 3F9000h SS24 3F8000h SS23 3F7000h SS22 3F6000h SS21 3F5000h SS20 3F4000h SS19 3F3000h SS18 3F2000h SS17 3F1000h SS16 3F0000h SS15 3EF000h SS14 ...

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Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts ...

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One byte Command Operation Command Code READ (03h) 0000 0011 FAST_READ (0Bh) 0000 1011 DOR (3Bh) 0011 1011 QOR (6Bh) 0110 1011 Read DIOR (BBh) 1011 1011 QIOR (EBh) 1110 1111 RDID (9Fh) 1001 1111 READ_ID (90h) 1001 0000 WREN ...

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Read Data Bytes (READ) The Read Data Bytes (READ) command reads data from the memory array at the frequency (f the SCK input, with a maximum speed of 40 MHz. The host system must first select the device by ...

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Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ command reads data from the memory array at the frequency (f input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# ...

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Dual Output Read Mode (DOR) The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at ...

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Quad Output Read Mode (QOR) The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 ...

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DUAL I/O High Performance Read Mode (DIOR) The Dual I/O High Performance Read instruction is similar to the Dual Output Read instruction, except that it improves throughput by allowing input of the address bits (A23-A0) using 2 bits per ...

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Figure 9.6 Continuous Dual I/O High Performance Read Instruction Sequence CS# SCK 22 SI/IO0 SO/IO1 23 October 5, 2009 S25FL032P_00_05 ...

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Quad I/O High Performance Read Mode (QIOR) The Quad I/O High Performance Read instruction is similar to the Quad Output Read instruction, except that it further improves throughput by allowing input of the address bits (A23-A0) using 4 bits ...

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Figure 9.8 Continuous QUAD I/O High Performance Instruction Sequence CS# SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 9.7 Read Identification (RDID) The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the ...

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Figure 9.9 Read Identification (RDID) Command Sequence and Data-Out Sequence Device S25FL032P SPI Flash Notes 1. Byte 0 is Manufacturer ID of Spansion. 2. Byte 1 & Device Id. 3. Byte 3 is Extended Device Information String Length, ...

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Table 9.5 Product Group CFI Device Geometry Definition Byte Data 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch October 5, 2009 ...

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Table 9.6 Product Group CFI Primary Vendor-Specific Extended Query Byte 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h Note CFI data related to V and time-outs may differ from actual V ...

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Read-ID (READ_ID) The READ_ID instruction provides the S25FL032P manufacturer and device information and is provided as an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. The instruction is ...

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Write Enable (WREN) The Write Enable (WREN) command (see enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Quad Page Program (QPP), Parameter ...

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Read Status Register (RDSR) The Read Status Register (RDSR) command outputs the state of the Status Register bits. the status register bits and their functions. The RDSR command may be written at any time, even while a program, erase, ...

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Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile, depending on the state ...

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Write Registers (WRR) The Write Registers (WRR) command allows changing the bits in the Status and Configuration Registers. A Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to ...

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Figure 9.16 Write Registers (WRR) Instruction Sequence – 16 data bits SCK SI SO W#/ SRWD ACC Bit Mode 1 1 Software 1 0 Protected (SPM Hardware 0 1 Protected (HPM) Note As defined ...

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Page Program (PP) The Page Program (PP) command changes specified bytes in the memory array (from only). A WREN command is required prior to writing the PP command. The host system must drive CS# low, and ...

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QUAD Page Program (QPP) The Quad Page Program instruction is similar to the Page Program instruction, except that the Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory ...

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Parameter Sector Erase (P4E, P8E) The Parameter Sector Erase (P4E, P8E) command sets all bits at all addresses within a specified sector to a logic 1 (FFh). A WREN command is required prior to writing the Parameter Sector Erase ...

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Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the SE command. The host system must drive CS# ...

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Bulk Erase (BE) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the BE command. The host system must drive CS# low, and ...

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Deep Power-Down (DP) The Deep Power-Down (DP) command provides the lowest power consumption mode of the device intended for periods when the device is not in active use, and ignores all commands except for the Release from ...

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Release from Deep Power-Down (RES) The device requires the Release from Deep Power-Down (RES) command to exit the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands except RES are ignored. The host system ...

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Release from Deep Power-Down and Read Electronic Signature (RES) The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.24 and Table 9.1 on page 23 Signature is not to be confused ...

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OTP Program (OTPP) The OTP Program command programs data in the OTP region, which different address space from the main array data. Refer to, Program command is the same as the Page Program command, except that ...

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OTP Regions The OTP Regions are separately addressable from the main array and consists of two 8-byte (ESN), thirty 16-byte, and one 10-byte regions that can be individually locked. The two 8-byte ESN region is a special order part ...

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ADDRESS 0x213h 0x204h 0x203h 0x1F4h 0x1F3h 0x1E4h 0x1E3 0x1D4h 0x1D3h 0x1C4h 0x1C3h 0x1B4h 0x1B3h 0x1A4h 0x1A3h 0x194h 0x193h 0x184h 0x183h 0x174h 0x173h 0x164h 0x163h 0x154h 0x153h 0x144h 0x143h 0x134h 0x133h 0x124h 0x123h 0x114h Bit 7 Bit 6 Bit 5 Bit ...

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ADDRESS 0x2FFh 0x2F6h 0x2F5h 0x2E6h 0x2E5 0x2D6h 0x2D5h 0x2C6h 0x2C5h 0x2B6h 0x2B5h 0x2A6h 0x2A5h 0x296h 0x295h 0x286h 0x285h 0x276h 0x275h 0x266h 0x265h 0x256h 0x255h 0x246h 0x245h 0x236h 0x235h 0x226h 0x225h 0x216h X Bit 6 Bit 5 Bit 4 Bit 3 ...

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Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied and must not be driven low to select the device until V CC (see Figure 11.1 and At ...

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Symbol V V CC(min (cut-off (low 12. Initial Delivery State The device is delivered with the memory array erased i.e. all ...

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Electrical Specifications 14.1 Absolute Maximum Ratings Description Ambient Storage Temperature Voltage with Respect to Ground: All Inputs and I/Os Output Short Circuit Current Note 1. Minimum DC voltage on input or I/Os is -0.5V. During voltage transitions, inputs or ...

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DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in on page 57, when relying on the quoted ...

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Test Conditions Input Levels Symbol C L 18. AC Characteristics Symbol (Notes) SCK Clock Frequency for READ command f R SCK Clock Frequency for RDID command SCK Clock Frequency for all others: f FAST_READ, PP, QPP, P4E, P8E, SE, ...

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Symbol (Notes) HOLD# Non Active Hold Time t CHHL (relative to SCK) t HOLD# enable to Output Invalid HZ t HOLD# disable to Output Valid LZ t W#/ACC Setup Time WPS t W#/ACC Hold Time WPH t WRR Cycle Time ...

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CS# SCK CS# SCK SO SI HOLD# Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1 W# CS# SCK SI Hi-Z SO October 5, 2009 S25FL032P_00_05 ...

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Physical Dimensions 19.1 SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width E1 PACKAGE SOC 008 (inches) SOC 008 (mm) JEDEC SYMBOL MIN ...

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SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) PACKAGE SO3 016 (inches) SO3 016 (mm) JEDEC MS-013(D)AA MS-013(D)AA SYMBOL MIN MAX MIN A 0.093 0.104 2.35 A1 0.004 0.012 0.10 A2 0.081 0.104 2.05 b ...

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USON 8-contact ( mm) No-Lead Package QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC DIMENSIONS SYMBOL MIN NOM e 1.27 BSC 0.55 0.60 b 0.35 0.40 D2 3.90 4.00 E2 3.30 3.40 ...

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WSON 8-contact ( mm) No-Lead Package D N 0.30 DIA TYP 0. TOP VIEW 2X 0. 0.05 C SEATING PLANE A1 L e/2 QUAD FLAT NO LEAD ...

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Ball Grid Array ( mm) Package (FAB024 S25FL032P S25FL032P_00_05 October 5, 2009 ...

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Ball Grid Array ( mm) Package (FAC024) PACKAGE FAC024 JEDEC N 8. 6.00 mm NOM PACKAGE SYMBOL MIN NOM A --- --- A1 0.25 --- A2 0.70 --- D 8.00 BSC. ...

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Revision History Section Revision 01 (June 9, 2008) Initial release. Revision 02 (February 12, 2009) Added USON package. Connection Diagrams Added Tray packing type. Valid Combinations Table Added OTP description for BPNV bit. Configuration Register Corrected TBPARM description. Configuration ...

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Section Release from Deep Power-Down (RES) Added note for RES command Updated descriptions OTP Regions Added ESN1 and ESN2 Table Operating Ranges Added Automotive In-cabin temperature range Added Automotive In-cabin spec for f AC Characteristics Updated t Physical Dimensions Added ...

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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2008-2009 Spansion Inc. All rights reserved. Spansion EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. ...