S29GL256P90FFIR10 Spansion Inc., S29GL256P90FFIR10 Datasheet
S29GL256P90FFIR10
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S29GL256P90FFIR10 Summary of contents
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S29GL-P MirrorBit S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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S29GL-P MirrorBit S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology Data Sheet (Preliminary) General Description The Spansion S29GL01G/512/256/128P are Mirrorbit offer a fast ...
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Performance Characteristics Density Voltage Range Regulated V 128 & 256 Mb VersatileIO V Regulated V 512 Mb VersatileIO V Regulated VersatileIO V Notes 1. Access times are dependent on V See Ordering Information Regulated ...
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Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 3.1 S29GL-P Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 2.1 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Ordering Information The ordering part number is formed by a valid combination of the following: S29GL01GP DEVICE NUMBER/DESCRIPTION S29GL01GP, S29GL512P, S29GL256P, S29GL128P 3.0 Volt-only, 1024, 512, 256 and 128 Megabit ...
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Recommended Combinations Recommended Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific recommended combinations and to check on newly released combinations. S29GL01GP S29GL512P S29GL256P, S29GL128P Notes 1. ...
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Input/Output Descriptions & Logic Symbol Table 2.1 identifies the input and output package connections provided on the device. Symbol Type A25–A0 Input DQ14–DQ0 I/O DQ15/A-1 I/O CE# Input OE# Input WE# Input V Supply CC ...
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Block Diagram RY/BY RESET# WE# State WP#/ACC Control BYTE# Command Register CE# OE# V Detector CC A **–A0 (A-1) Max ** A GL01GP=A25, A GL512P = A24, A Max Max Max 4. Physical ...
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RFU A7 A13 WE# RESET# A4 RY/BY# WP#/ACC RFU Note RFU = No Connect (NC) November 8, 2007 S29GL-P_00_A7 ...
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LAA064—64 ball Fortified Ball Grid Array Figure 4.2 LAA064—64ball Fortified Ball Grid Array (FBGA ...
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A23 1 A22 2 A15 3 A14 4 A13 5 A12 6 A11 7 A10 A19 11 A20 12 WE# 13 RESET# 14 A21 15 WP#/ACC 16 RY/BY# 17 A18 18 ...
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TS056—56-Pin Standard Thin Small Outline Package (TSOP) Figure 4.4 56-Pin Thin Small Outline Package (TSOP PACKAGE TS 56 JEDEC MO-142 (B) EC SYMBOL MIN. NOM. MAX. A --- --- 1.20 A1 0.05 --- 0.15 A2 ...
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Additional Resources Visit www.spansion.com 5.1 Application Notes The following is a list of application notes related to this product. All Spansion application notes are available at http://www.spansion.com/support/technical_documents/application_notes.html Using the Operation Status Bits in AMD Devices ...
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Product Overview The S29GL-P family consists of 1 Gb, 512 Mb, 256 Mb and 128 Mb, 3.0-volt-only, page mode Flash devices optimized for today’s embedded designs that demand a large storage array and rich functionality. These devices are manufactured ...
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Uniform Sector Size 64 Kword/128 Kb Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as ...
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Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled ...
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7.6 Autoselect The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes output from the internal register (separate from the memory array) on DQ7-DQ0. This mode is primarily intended for programming ...
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Table 7.2 Autoselect Codes, (High Voltage Method) Description CE# OE# WE# Manufacturer ID Spansion Product Cycle 1 Cycle Cycle 3 Cycle 1 Cycle Cycle 3 Cycle 1 Cycle 2 ...
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Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Software Functions and Sample Code Cycle Unlock Cycle 1 Note 1. Any offset within the device works. 2. base = base address. The following ...
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Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. During a write operation, the system must drive CE# and WE command, and ...
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PASS. Device is in November 8, 2007 S29GL-P_00_A7 Figure 7.1 Single Word Program Write Unlock Cycles: Address 555h, ...
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Software Functions and Sample Code Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note Base = Base Address. The following source code example of using the single word program function. Refer to the Spansion Low ...
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The write-buffer “embedded” programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED under ...
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Software Functions and Sample Code (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle Description Write Buffer Load Command 4 Write Word Count Number of words (N) loaded into the write buffer can be from words ...
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Write Next Word, Decrement wc – 1 RESET. Issue Write Buffer Abort Reset Command November 8, 2007 S29GL-P_00_A7 ...
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Sector Erase The sector erase function erases one or more sectors in the memory array. (See Figure 7.3.) The device does not require the system to preprogram a sector prior to erase. The Embedded Erase algorithm automatically programs and ...
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h Select No Additional Sectors? Yes ...
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Chip Erase Command Sequence Chip erase is a six-bus cycle operation as indicated by Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory ...
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7.7.5 Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The sector address ...
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Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation or a “Write to Buffer” programming operation so that data can read from any non-suspended sector. When the Program Suspend command is ...
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7.7.7 Accelerated Program Accelerated single word programming and write buffer programming operations are enabled through the WP#/ACC pin. This method is faster than the standard program command sequences. Note The accelerated program functions must not be ...
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Cycle 1 Program Setup Command 2 Program Command /* Example: Unlock Bypass Program Command /* Do while in Unlock Bypass Entry Mode! *( (UINT16 *)base_addr ) = 0x00A0; *( (UINT16 *) Poll until done or error ...
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the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at ...
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this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memory sectors not possible to temporarily prevent reads to other memory sectors, ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Program Program- Suspend Suspend Mode Read Erase- Suspend Erase Read Suspend Mode Erase-Suspend-Program (Embedded Program) Write-to- Buffer Notes 1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer ...
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7.9.3 Software Reset Software reset is part of the command set (see read mode and must be used for the following conditions exit Autoselect mode 2. when DQ5 goes high during write status operation ...
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Advanced Sector Protection/Unprotection The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the ...
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8.1 Lock Register As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see on page 9). ...
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There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 9. Exit command must be issued after the execution which resets the device to read mode and re- enables ...
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8.2.1 Dynamic Protection Bits Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to “1”). ...
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There is no means to verify what the password is after it is set. 6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7. The Password Mode ...
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Enter Lock Register Command: Address 555h, Data 40h Program Lock Register Data Address XXXh, Data A0h Address XXXh*, Data PD Perform Polling Algorithm (see Write ...
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Advanced Sector Protection Software Examples Table 8.2 Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations Unique Device PPB Lock Bit 0 = locked 1 = unlocked Any Sector Any Sector Any Sector Any Sector Any Sector Any ...
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8.6.3 Write Pulse “Glitch Protection” Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 8.6.4 Power-Up Write Inhibit If WE# = CE# = RESET ...
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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 128 words in length and all Secured ...
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Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0. 10.3 Secured Silicon Sector ...
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Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle 3 Exit Cycle 4 Note Base = Base Address. /* Example: SecSi Sector Exit Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; *( (UINT16 *)base_addr + 0x2AA ) = ...
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11.2 Operating Ranges Ambient Temperature (TA), Industrial (I) Device Supply Voltages V Supply Voltages IO Notes 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. See also Ordering Information ...
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Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels Note If V < the reference level is 0.5 ...
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11.6 DC Characteristics Table 11.2 S29GL-P DC Characteristics (CMOS Compatible) Parameter Parameter Description Symbol (Notes) I Input Load Current ( Input Load Current LIT I Output Leakage Current Active Read ...
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AC Characteristics 11.7.1 S29GL-P Read-Only Operations Parameter Description JEDEC Std. (Notes Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time ...
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Addresses CE# OE# WE# Outputs RESET# RY/BY Amax:A3 A2:A0 (See Note) Data Bus CE# OE# Note Figure 11.6 shows word mode. Addresses are A2:A-1 for byte mode. November 8, 2007 S29GL-P_00_A7 ...
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Hardware Reset (RESET#) Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms Ready Read Mode or Write mode RESET# Pin Low (NOT During Embedded Algorithms) t Ready to Read Mode or Write mode t RESET# Pulse Width ...
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Parameter Reset Low Time from rising edge VCS rising edge of RESET# Reset Low Time from rising edge VIOS rising edge of RESET# t Reset High Time before Read RH ...
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S29GL-P Erase and Program Operations Table 11.6 S29GL-P Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low ...
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Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data, D OUT 2. Illustration shows ...
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Figure 11.11 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector ...
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Figure 11.13 Toggle Bit Timings (During Embedded Algorithms) Addresses CE# t OEH WE# OE Valid Data DQ2 and DQ6 RY/BY# Note A = Valid address; not required for DQ6. Illustration shows first two status ...
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S29GL-P Alternate CE# Controlled Erase and Program Operations Table 11.7 S29GL-P Alternate CE# Controlled Erase and Program Operations Parameter Description JEDEC Std. (Notes Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS ...
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Figure 11.15 Alternate CE# Controlled Write (Erase/Program) Operation Timings 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes 1. Figure 11.15 indicates last ...
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Erase And Programming Performance Table 11.8 Erase And Programming Performance Parameter Sector Erase Time S29GL128P S29GL256P Chip Erase Time S29GL512P S29GL01GP Total Write Buffer Time (Note 3) Total Accelerated Write Buffer Programming Time (Note 3) S29GL128P S29GL256P Chip Program ...
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12. Appendix This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see the Spansion web site at www.spansion.com. 12.1 Command Definitions Writing specific address ...
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Table 12.1 S29GL-P Memory Array Command Definitions, x16 Command (Notes) Read (6) Reset (7) Manufacturer ID Device ID (8) Sector Protect Verify (10) Secure Device Verify (11) CFI Query (12) Program Write to Buffer Program Buffer to Flash (Confirm) Write-to-Buffer-Abort ...
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Table 12.2 S29GL-P Sector Protection Command Definitions, x16 Command (Notes) Command Set Entry 3 Program (6) 2 Read (6) 1 Command Set Exit ( Command Set Entry 3 Password Program (9) 2 Password Read ...
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Table 12.3 S29GL-P Memory Array Command Definitions, x8 Command (Notes) Read (6) 1 Reset (7) 1 Manufacturer ID 4 Device ID (8) 4 Sector Protect Verify (10) 4 Secure Device Verify (11) 4 CFI Query (12) 1 Program Write to ...
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Table 12.4 S29GL-P Sector Protection Command Definitions, x8 Command (Notes) Command Set Entry 3 Bits Program (6) 2 Read (6) 1 Command Set Exit ( Command Set Entry 3 Password Program (9) 2 Password ...
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Common Flash Memory Interface The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ...
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Addresses (x16) Addresses (x8) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses (x16) Addresses (x8) 27h 4Eh 28h 50h ...
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Table 12.8 Primary Vendor-Specific Extended Query Addresses (x16) Addresses (x8) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah 4Eh 9Ch ...
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13. Advance Information on S29GL MirrorBit Hardware Reset (RESET#) and Power-up Sequence Parameter t RESET# Low to CE# Low RPH t RESET# Pulse Width RP t Time between RESET# (high) and CE# (low) RH ...
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Revision History Section Revision A0 (October 29, 2004) Initial Release. Revision A1 (October 20, 2005) Global Revised all sections of document. Revision A2 (October 19, 2006) Revised all sections of document. Reformatted document to new template. Changed speed options ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004–2007 Spansion Inc. All rights reserved. Spansion ™ SIM and combinations thereof, are trademarks of Spansion LLC in the US and other countries ...