STM32F100ZET6B STMicroelectronics, STM32F100ZET6B Datasheet

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STM32F100ZET6B

Manufacturer Part Number
STM32F100ZET6B
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F100ZET6B

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Features
April 2011
256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces
Core: ARM 32-bit Cortex™-M3 CPU
– 24 MHz maximum frequency, 1.25 DMIPS
– Single-cycle multiplication and hardware
Memories
– 256 to 512 Kbytes of Flash memory
– 24 to 32 Kbytes of SRAM
– Flexible static memory controller with 4
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
– 4-to-24 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
Serial wire debug (SWD) and JTAG I/F
DMA
– 12-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
1 × 12-bit, 1.2 µs A/D converter (up to 16 ch.)
– Conversion range: 0 to 3.6 V
– Temperature sensor
2 × 12-bit D/A converters
Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
/MHz (Dhrystone 2.1) performance
division
Chip Selects. Supports SRAM, PSRAM
and NOR memories
detector (PVD)
I
external interrupt vectors and almost all
5 V-tolerant
2
High-density value line, advanced ARM-based 32-bit MCU with
BAT
Cs, USARTs and DACs
supply for RTC and backup registers
Doc ID 15081 Rev 5
STM32F100xD STM32F100xE
Table 1.
STM32F100xC
STM32F100xD
STM32F100xE
Up to 16 timers
– Up to seven 16-bit timers, each with up to 4
– One 16-bit, 6-channel advanced-control
– One 16-bit timer, with 2 IC/OC, 1
– Two 16-bit timers, each with
– Two watchdog timers
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
Up to 11 communications interfaces
– Up to two I
– Up to 3 USARTs (ISO 7816 interface, LIN,
– Up to 2 UARTs
– Up to 3 SPIs (12 Mbit/s)
– Consumer electronics control (CEC) I/F
CRC calculation unit, 96-bit unique ID
Reference
20 × 20 mm
LQFP144
IC/OC/PWM or pulse counter
timer: up to 6 channels for PWM output,
dead time generation and emergency stop
OCN/PWM, dead-time generation and
emergency stop
IC/OC/OCN/PWM, dead-time generation
and emergency stop
IrDA capability, modem control)
Device summary
STM32F100RC, STM32F100VC,
STM32F100ZC
STM32F100RD, STM32F100VD,
STM32F100ZD
STM32F100RE, STM32F100VE,
STM32F100ZE
2
C interfaces (SMBus/PMBus)
STM32F100xC
14 × 14 mm
LQFP100
Part number
10 × 10 mm
LQFP64
www.st.com
1/97
1

Related parts for STM32F100ZET6B

STM32F100ZET6B Summary of contents

Page 1

High-density value line, advanced ARM-based 32-bit MCU with 256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 24 MHz maximum frequency, 1.25 DMIPS /MHz (Dhrystone 2.1) performance – ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F100xC, STM32F100xD, STM32F100xE 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 6.2.1 6.2.2 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ...

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STM32F100xC, STM32F100xD, STM32F100xE List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 45. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STM32F100xC, STM32F100xD, STM32F100xE List of figures Figure 1. STM32F100xx value line block diagram Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . ...

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... STM32F100xx high-density value line Flash programming manual (PM0072). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter ...

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STM32F100xC, STM32F100xD, STM32F100xE 2 Description The STM32F100xx value line family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM Kbytes), a ...

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Description 2.1 Device overview Table 2. STM32F100xx features and peripheral counts Peripheral Flash - Kbytes SRAM - Kbytes FSMC Advanced-control Timers General-purpose SPI Communication USART interfaces UART CEC 12-bit synchronized ADC number of channels GPIOs 12-bit DAC ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 1. STM32F100xx value line block diagram TRACECLK TRACED[0:3] JTAG & NJTRST JTDI Cortex-M3 CPU JTCK/SWCLK JTMS/SWDIO JTDO MHz max as AF NVIC A[25:0] D[15:0] GP DMA CLK NOE 12 channels ...

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Description Figure 2. Clock tree 1. To obtain an ADC conversion time of 1.2 µs, APB2 must MHz. 12/97 STM32F100xC, STM32F100xD, STM32F100xE Doc ID 15081 Rev 5 ...

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STM32F100xC, STM32F100xD, STM32F100xE 2.2 Overview ® 2.2.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets ...

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Description specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost- effective graphic applications using LCD modules with embedded controllers or high- performance solutions using external controllers with dedicated acceleration. 2.2.7 Nested vectored interrupt controller (NVIC) ...

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STM32F100xC, STM32F100xD, STM32F100xE The boot loader is located in System Memory used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.2.11 Power supply schemes ● 2.0 to 3.6 V: ...

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Description either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 3. Timer feature comparison Counter Timer resolution TIM1 16-bit TIM2, TIM3, 16-bit TIM4, TIM5 TIM12 16-bit TIM13, 16-bit TIM14 TIM15 16-bit TIM16, 16-bit TIM17 TIM6, 16-bit TIM7 Warning: The advanced-control timer (TIM1) can be seen as ...

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Description General-purpose timers (TIM2..5, TIM12..17) There are ten synchronizable general-purpose timers embedded in the STM32F100xx devices (see Table 3 PWM outputs simple time base. TIM2, TIM3, TIM4, TIM5 STM32F100xx devices feature four synchronizable 4-channel general-purpose timers. These timers ...

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STM32F100xC, STM32F100xD, STM32F100xE management hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. ...

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Description 2.2.21 Serial peripheral interface (SPI three SPIs are able to communicate Mbit/s in slave and master modes in full- duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the ...

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STM32F100xC, STM32F100xD, STM32F100xE 2.2.25 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier ...

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Pinouts and pin descriptions 3 Pinouts and pin descriptions Figure 3. STM32F100xx value line LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 4. STM32F100xx value line LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

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Pinouts and pin descriptions Figure 5. STM32F100xx value line in LQFP64 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT Table 4. High-density STM32F100xx pin definitions Pins Pin name ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 4. High-density STM32F100xx pin definitions (continued) Pins Pin name ...

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Pinouts and pin descriptions Table 4. High-density STM32F100xx pin definitions (continued) Pins Pin name ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 4. High-density STM32F100xx pin definitions (continued) Pins Pin name ...

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Pinouts and pin descriptions Table 4. High-density STM32F100xx pin definitions (continued) Pins Pin name 100 67 41 101 68 42 102 69 ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 4. High-density STM32F100xx pin definitions (continued) Pins Pin name 120 - - V 121 - - V 122 87 - 123 88 - 124 - - 125 - - 126 - - 127 - - 128 ...

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... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com. 8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 5. FSMC pin definition (continued) Pins PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PD0 PD1 PD3 ...

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Memory mapping Table 5. FSMC pin definition (continued) Pins PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 1. Ports F and G are not available in devices delivered in 100-pin packages. 4 Memory mapping The memory map is ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 6. Memory map 0xFFFF FFFF 7 0xE010 0000 Cortex-M3 internal peripherals 0xE000 0000 6 0xC000 0000 5 FSMC regs 0xA000 0000 4 0x8000 0000 0x7000 0000 3 FSMC external memory 0x6000 0000 2 Peripherals 0x4000 0000 ...

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Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 7. Pin loading conditions 5.1.6 Power supply scheme Figure 9. Power supply scheme 1.8-3.6V 5 × 100 × 4.7 μ μF ...

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Electrical characteristics 5.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Current characteristics, and damage to the device. These are stress ratings only and functional ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 7. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control ...

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Electrical characteristics Table 9. General operating conditions (continued) Symbol Power dissipation °C for suffix 105 °C for suffix 7 Ambient temperature for 6 suffix version T A Ambient temperature for 7 suffix ...

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STM32F100xC, STM32F100xD, STM32F100xE 5.3.3 Embedded reset and power control block characteristics The parameters given in temperature and V . Table 11. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis ...

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Electrical characteristics 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 12. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal S_vrefint reference voltage Internal reference voltage ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply I current in DD Run mode 1. Based on characterization, not tested in production. 2. External clock or HSI ...

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Electrical characteristics Table 15. STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock or HSI ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 16. Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high- speed oscillator OFF (no independent watchdog) Supply current in Stop mode ...

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Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply I current in DD Run mode 1. Typical values are measures Add an additional power consumption of ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Typical values are measures Add an additional power consumption of ...

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Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● all I/O pins are in input mode with a static value at V ● all peripherals are disabled unless ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 19. Peripheral current consumption (continued) Peripheral GPIO A GPIO B GPIO C GPIO D GPIO E GPIO F GPIO G APB2 ADC1 SPI1 USART1 TIM1 TIM15 TIM16 TIM17 HCLK APB1 ...

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Electrical characteristics Table 20. High-speed external user clock characteristics Symbol DuCy Duty cycle (HSE) I OSC_IN Input leakage current L 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 11. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 12. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) ...

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Electrical characteristics Table 22. HSE 4-24 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C L1 versus equivalent serial ( resistance of the crystal (R i HSE driving current 2 g ...

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STM32F100xC, STM32F100xD, STM32F100xE Note: For C and recommended to use high-quality ceramic capacitors in the range selected to match the requirements of the crystal or resonator. C usually the same ...

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Electrical characteristics Figure 14. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors 5.3.7 Internal clock source characteristics The parameters given in temperature and V High-speed internal (HSI) RC oscillator Table 24. HSI oscillator ...

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STM32F100xC, STM32F100xD, STM32F100xE Wakeup time from low-power mode The wakeup times given in RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● Stop or Standby mode: the clock source is the ...

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Electrical characteristics 5.3.9 Memory characteristics Flash memory The characteristics are given at T Table 28. Flash memory characteristics Symbol t 16-bit programming time prog t Page (2 KB) erase time ERASE t Mass erase time ME I Supply current DD ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Doc ID 15081 Rev 5 Electrical characteristics 55/97 ...

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Electrical characteristics Table 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low time w(NOE) t FSMC_NOE high to FSMC_NE high hold time –1.5 h(NE_NOE) t FSMC_NEx low ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t ...

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Electrical characteristics Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 32. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 33. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE ...

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Electrical characteristics Synchronous waveforms and timings Figure 19 through Table 37 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 34. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV ...

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Electrical characteristics Figure 20. Synchronous multiplexed PSRAM write timings 62/97 STM32F100xC, STM32F100xD, STM32F100xE Doc ID 15081 Rev 5 ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 35. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t ...

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Electrical characteristics Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings Table 36. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 22. Synchronous non-multiplexed PSRAM write timings Table 37. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t su(NWAITV-CLKH) ...

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Electrical characteristics 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by ...

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STM32F100xC, STM32F100xD, STM32F100xE Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the ...

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Electrical characteristics 5.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. However, ...

Page 69

STM32F100xC, STM32F100xD, STM32F100xE 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 43. I/O static characteristics Symbol Parameter Standard I/O input low level voltage V IL (1) ...

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Electrical characteristics Figure 23. Standard I/O input characteristics - CMOS port Figure 24. Standard I/O input characteristics - TTL port 70/97 STM32F100xC, STM32F100xD, STM32F100xE Doc ID 15081 Rev 5 ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 25 tolerant I/O input characteristics - CMOS port Figure 26 tolerant I/O input characteristics - TTL port Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, ...

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Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 9. All I/Os are CMOS and TTL compliant. Table 44. Output voltage characteristics Symbol Output Low level voltage for ...

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STM32F100xC, STM32F100xD, STM32F100xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 45, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 9. Table 45. I/O ...

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Electrical characteristics Figure 27. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved ≤ 2/3)T and if the duty cycle is (45-55%) 5.3.15 NRST pin characteristics The NRST pin ...

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STM32F100xC, STM32F100xD, STM32F100xE 5.3.16 TIMx characteristics The parameters given in Refer to Section 5.3.13: I/O current injection characteristics alternate function characteristics (output compare, input capture, external clock, PWM output). Table 47. TIMx characteristics Symbol t Timer resolution time res(TIM) Timer ...

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Electrical characteristics 2 Table 48 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...

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STM32F100xC, STM32F100xD, STM32F100xE 2 Figure 29 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 49. SCL frequency ( External pull-up resistance For speeds around ...

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Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in from tests performed under the ambient temperature, f voltage conditions summarized in Refer to Section 5.3.13: I/O current injection characteristics input/output alternate function characteristics (NSS, SCK, MOSI, MISO). ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 30. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT ...

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Electrical characteristics Figure 32. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V HDMI ...

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STM32F100xC, STM32F100xD, STM32F100xE Table 51. ADC characteristics Symbol Parameter V Power supply DDA V Positive reference voltage REF+ Current on the V input REF I VREF pin f ADC clock frequency ADC (2) Sampling rate f S (2) f External ...

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Electrical characteristics Table 52. R AIN T (cycles) s 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 1. Guaranteed by design, not tested in production. Table 53. ADC accuracy - limited test conditions Symbol ET Total unadjusted error EO Offset ...

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STM32F100xC, STM32F100xD, STM32F100xE Any positive injection current within the limits specified for I Section 5.3.13 does not affect the ADC accuracy. Figure 33. ADC accuracy characteristics V [1LSB = IDEAL 4095 4094 4093 ...

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Electrical characteristics Figure 35. Power supply and reference decoupling (V 1 µ available on 100-pin packages and on TFBGA64 packages. V REF+ packages only. Figure 36. Power supply and reference decoupling ( ...

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STM32F100xC, STM32F100xD, STM32F100xE 5.3.19 DAC electrical specifications Table 55. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (1) R Resistive load with buffer ON LOAD (1) R Impedance output with buffer ...

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Electrical characteristics Table 55. DAC characteristics (continued) Symbol Parameter Offset error (difference between measured value (1) Offset at Code (0x800) and the ideal value = V /2) REF+ Gain Gain error (1) error Settling time (full scale: for a 10-bit ...

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STM32F100xC, STM32F100xD, STM32F100xE 5.3.20 Temperature sensor characteristics Table 56. TS characteristics Symbol ( linearity with temperature L SENSE (1) Avg_Slope Average slope (1) V Voltage at 25°C 25 (2) t Startup time START (3)(2) T ADC sampling time ...

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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 38. LQFP144 mm, 144-pin thin quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to ...

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Package characteristics Figure 40. LQFP100 – mm, 100-pin low-profile quad flat package outline 100 26 Pin identification e 1. Drawing is not to scale. 2. Dimensions are ...

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STM32F100xC, STM32F100xD, STM32F100xE Figure 42. LQFP64 – mm, 64 pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 59. LQFP64 – ...

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Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 9: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ ...

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STM32F100xC, STM32F100xD, STM32F100xE 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, ...

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Package characteristics Using the values obtained in – For LQFP100, 40 °C 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C Jmax This is within the range of the suffix ...

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STM32F100xC, STM32F100xD, STM32F100xE 7 Ordering information scheme Table 61. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Device subfamily 100 = value line Pin count pins V = 100 ...

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Revision history 8 Revision history Table 62. Document revision history Date 09-Oct-2008 31-Mar-2009 01-Sep-2010 18-Oct-2010 11-Apr-2011 96/97 STM32F100xC, STM32F100xD, STM32F100xE Revision 1 Initial release. I/O information clarified on page 1. Table 5: High-density STM32F100xx pin definitions modified. Figure 5: Memory ...

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... STM32F100xC, STM32F100xD, STM32F100xE Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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