SY10EL34ZG TR Micrel Inc, SY10EL34ZG TR Datasheet
SY10EL34ZG TR
Manufacturer Part Number
SY10EL34ZG TR
Description
3.3V /2, /4, /8 Clock Generation Chip (I Temp, Green)
Manufacturer
Micrel Inc
Series
10EL, Precision Edge®r
Type
Clock Generatorr
Datasheet
1.SY100EL34LZG.pdf
(5 pages)
Specifications of SY10EL34ZG TR
Pll
No
Input
ECL, PECL
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
Yes/Yes
Divider/multiplier
Yes/No
Voltage - Supply
4.75 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Number Of Outputs
6
Operating Supply Voltage (max)
-5.5V
Operating Temp Range
-40C to 85C
Propagation Delay Time
1.2ns
Operating Supply Voltage (min)
-4.75V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
-5V
Package Type
SOIC
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
Lead Free Status / Rohs Status
Compliant
Other names
SY10EL34ZGTR
SY10EL34ZGTR
SY10EL34ZGTR
Micrel, Inc.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-031006
hbwhelp@micrel.com or (408) 955-1690
FEATURES
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master Reset for synchronization
Internal 75K input pull-down resistors
Available in 16-pin SOIC package
PIN NAMES
CLK
EN
MR
V
Q
Q
Q
Pin
BB
0
1
2
Differential Clock Inputs
Synchronous Enable
Master Reset
Reference Output
Differential 2 Outputs
Differential 4 Outputs
Differential 8 Outputs
Function
5V/3.3V 2, 4, 8 CLOCK
GENERATION CHIP
1
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
coupled into the device. If a single-ended input is to be
used, the V
input and bypassed to ground via a 0.01 F capacitor.
The V
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
DESCRIPTION
The SY10/100EL34/L are low skew
The common enable (EN) is synchronous so that the
Upon start-up, the internal flip-flops will attain a random
BB
output is designed to act as the switching
BB
BB
output should be connected to the CLK
output, a sinusoidal source can be AC-
Precision Edge
SY100EL34/L
Precision Edge
Rev.: H
Issue Date: March 2006
SY10EL34/L
2,
Precision Edge
SY100EL34/L
4, 8 clock
SY10EL34/L
Amendment: /0
®
®
®
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SY10EL34ZG TR Summary of contents
Page 1
Micrel, Inc. FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 16-pin SOIC package PIN NAMES Pin Function CLK Differential Clock Inputs EN Synchronous Enable MR ...
Page 2
Micrel, Inc. PACKAGE/ORDERING INFORMATION ÷ CLK 1 Q ÷ CLK ...
Page 3
Micrel, Inc. TRUTH TABLE CLK NOTE LOW-to-HIGH transition ZZ = HIGH-to-LOW transition DC ELECTRICAL CHARACTERISTICS (Min (Max.); ...
Page 4
Micrel, Inc. TIMING DIAGRAM CLK The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal ...
Page 5
Micrel, Inc. 16-PIN SOIC .150" WIDE (Z16-2) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility ...