XR17D154IV Exar Corporation, XR17D154IV Datasheet

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XR17D154IV

Manufacturer Part Number
XR17D154IV
Description
Universal QUART W/ PCI Bus Interface.
Manufacturer
Exar Corporation
Datasheet

Specifications of XR17D154IV

Features
*
Number Of Channels
4, QUART
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant

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xr
AUGUST 2005
GENERAL DESCRIPTION
The XR17D154
Asynchronous Receiver and Transmitter (UART) with
same package and pin-out as the Exar XR17C158,
XR17D158 and XR17C154. The device is designed
to meet today’s 32-bit PCI Bus and high bandwidth
requirement in communication systems. The global
interrupt source register provides a complete interrupt
status indication for all 4 channels to speed up
interrupt parsing. Each UART is independently
controlled and has its own 16C550 compatible 5G
register set, transmit and receive FIFOs of 64 bytes,
fully programmable transmit and receive FIFO trigger
levels, transmit and receive FIFO level counters,
automatic hardware flow control with programmable
hysteresis,
control, IrDA (Infrared Data Association) encoder/
decoder, 8 multi-purpose inputs/outputs and a 16-bit
general purpose timer/counter.
N
APPLICATIONS
Exar
F
OTE
IGURE
Universal Form Factor PCI Bus Add-in Card
Remote Access Servers
Ethernet Network to Serial Ports
Network Management
Factory Automation and Process Control
Point-of-Sale Systems
Multi-port RS-232/RS-422/RS-485 Cards
:
Corporation 48720 Kato Road, Fremont CA, 94538
1 Covered by U.S. Patents #5,649,122, #5,949,787
1. B
LOCK
automatic
Power Supply)
CLK (33MHz)
3.3V or 5V
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
IDSEL
PERR#
SERR#
PAR
EECK
EEDI
EEDO
EECS
ENIR
(PCI VI/O
1
(D154) is a quad PCI Bus Universal
D
IAGRAM
software
Configuration
EEPROM
PCI Local
Registers
Interface
Interface
Space
Bus
(Xon/Xoff)
Timer/Counter
Configuration
16-bit
Registers
Device
flow
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
(510) 668-7000
FEATURES
High Performance Quad PCI UART
Universal PCI Bus Buffers - Auto-sense 3.3V or 5V
Operation
32-bit PCI Bus 2.3 Target Signalling Compliance
A Global Interrupt Source Register for all 4 UARTs
Data Transfer in Byte, Word and Double-word
Data Read/Write Burst Operation
Each UART is independently controlled with:
Eight Multi-Purpose Inputs/outputs
General Purpose 16-bit Timer/Counter
Sleep Mode with Automatic Wake-up
EEPROM Interface for PCI Configuration
Same package and pin-out as the XR17D158,
XR17C158 and
LQFP)
UART
Regs
BRG
16C550 Compatible 5G Register Set
64-byte Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Automatic RTS/CTS or DTR/DSR Flow Control
Automatic Xon/Xoff Software Flow Control
Automatic RS485 Half-duplex Control Output
with Selectable Turn-around Delay
Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
Up to 6.25 Mbps Serial Data Rate at 8X
UART Channel 3
UART Channel 0
UART Channel 2
Crystal Osc/Buffer
UART Channel 1
Inputs/Outputs
Multi-purpose
TX & RX
64 Byte RX FIFO
64 Byte TX FIFO
FAX (510) 668-7017
.
ENDEC
IR
XR17C154 (20x20x1.4mm 144-
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
MPIO0- MPIO7
XTAL1
XTAL2
TMRCK
GND
VCC (Core
Logic)
www.exar.com
REV. 1.2.2

Related parts for XR17D154IV

XR17D154IV Summary of contents

Page 1

AUGUST 2005 GENERAL DESCRIPTION 1 The XR17D154 (D154 quad PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with same package and pin-out as the Exar XR17C158, XR17D158 and XR17C154. The device is designed to meet today’s 32-bit ...

Page 2

... AD31 AD30 139 AD29 140 AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION ART UMBER ACKAGE XR17D154CV 144-Lead LQFP XR17D154IV 144-Lead LQFP XR17D154 144-LQFP PERATING EMPERATURE ANGE 0°C to +70°C -40°C to +85° REV. 1.2 ENIR 70 69 TMRCK ...

Page 3

REV. 1.2.2 PIN DESCRIPTIONS AME IN PCI LOCAL BUS INTERFACE RST# 134 CLK 135 AD31-AD25, 138-144, AD24, 1, AD23-AD16, 6-13 AD15-AD8, 26-33 AD7-AD0 37-44 FRAME# 15 C/BE3#- 2,14,25,36 C/BE0# IRDY# 16 TRDY# 17 STOP# 21 ...

Page 4

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART PIN DESCRIPTIONS AME IN TX1 106 RX1 99 RTS1# 104 CTS1# 100 DTR1# 105 DSR1# 101 CD1# 102 RI1# 103 TX2 88 RX2 81 RTS2# 86 CTS2# ...

Page 5

REV. 1.2.2 PIN DESCRIPTIONS AME IN MPIO1 107 MPIO2 74 MPIO3 73 MPIO4 68 MPIO5 67 MPIO6 66 MPIO7 65 EECK 116 EECS 115 EEDI 114 EEDO 113 XTAL1 110 XTAL2 109 TMRCK 69 ENIR ...

Page 6

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART PIN DESCRIPTIONS AME IN VIO 4, 19, 34, 45, 137 PWR GND 5,20,35,46,63, PWR 89,136 NC 47-54, 71, 72, 75-80, 91-98, 117-124 N : Pin type: I=Input, ...

Page 7

REV. 1.2.2 FUNCTIONAL DESCRIPTION The XR17D154 (D154) integrates the functions of 4 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose inputs/outputs, and an ...

Page 8

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 1.0 APPLICATION EXAMPLES The XR17D154 is designed to operate with VCC (voltage to the UART Core Logic) greater than or equal to VIO. See Table 1 below for valid combintions of ...

Page 9

REV. 1.2 IGURE YPICAL PPLICATIONS IN AN Example 1 VIO = 3.3V, VCC = 5V Example 2 VIO = 5V, VCC = 5V Example 3 VIO = 3.3V, VCC = 3.3V UNIVERSAL (3.3V AND 5V) ...

Page 10

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 2.0 XR17D154 REGISTERS The XR17D154 UART has three different sets of registers as shown in configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This ...

Page 11

REV. 1.2 PCI L ABLE DDRESS ITS YPE 0x00 31:16 Device ID (Exar device ID number or from EEPROM) 1 RWR 15:0 Vendor ID (Exar ID or from EEPROM) specified by PCISIG 1 RWR ...

Page 12

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART T 2: PCI L ABLE DDRESS ITS YPE 15:0 1 Subsystem Vendor ID (write from external EEPROM by cus- RWR tomer) 0x30 31:0 RO Expansion ROM Base Address ...

Page 13

REV. 1.2 XR17D154 D ABLE O FFSET M S EMORY PACE A DDRESS 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 - 0x0FF Reserved 0x100 - 0x13F ...

Page 14

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART ABLE EVICE A DDRESS R EGISTER [A7:A0] Ox080 INT0 [7:0] Ox081 INT1 [15:8] Ox082 INT2 [23:16] Ox083 INT3 [31:24] Ox084 TIMERCNTL Ox085 TIMER Ox086 TIMERLSB Ox087 TIMERMSB Ox088 ...

Page 15

REV. 1.2.2 2.2.1 The Interrupt Status Register The XR17D154 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme uses bits 8-bit ...

Page 16

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART Registers INT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bit [10:8] represent channel 0 and ...

Page 17

REV. 1.2.2 T ABLE RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level. RXRDY Time-out is cleared by reading data until the RX FIFO is empty. RX Line Status interrupt clears ...

Page 18

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Rsvd TIMER [15:8] - Reserved TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being ...

Page 19

REV. 1.2.2 2.2.6 SLEEP [31:24] - (default 0x00) Each UART can be separately enabled to enter Sleep mode through the Sleep register. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. All of ...

Page 20

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 2.2.7 Device Identification and Revision There are two internal registers that provide device identification and revision, DVID and DREV registers. The 8-bit content in the DVID register provides device identification. A ...

Page 21

REV. 1.2.2 2.2.10 MPIO REGISTER Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs pins IGURE ULTIPURPOSE INPUT MPIOINT ...

Page 22

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART MPIOLVL [7:0] - (default 0x00) Output pin level control and input level status. The status of the input pin(s) is read on this register and output pins are controlled on this ...

Page 23

REV. 1.2.2 3.0 CRYSTAL OSCILLATOR / BUFFER The D154 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the 4 UARTs, the 16-bit general purpose ...

Page 24

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 4.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data ...

Page 25

REV. 1.2 FIFO, EAD B YTE WITH RRORS Read n+0 to n+3 FIFO Data n+3 Read n+4 to n+7 FIFO Data n+7 Etc. Channel ReceiveData in 32-bit alignment through the Configuration ...

Page 26

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 4.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700 The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation ...

Page 27

REV. 1.2.2 5.0 UART There are 4 UARTs [channels 3:0] in the D154. Each has its own 64-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate generator for individual ...

Page 28

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART T 10: T ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7=0 100 400 600 2400 1200 4800 2400 9600 4800 19.2k ...

Page 29

REV. 1.2 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) 5.2.3 Transmitter Operation in FIFO mode The host may fill the transmit FIFO with up to ...

Page 30

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 5.3 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X or 8X clock for timing. It verifies and validates ...

Page 31

REV. 1.2.2 5.3.3 Receiver Operation with FIFO F 15 IGURE ECEIVER PERATION IN 16X or 8X Sampling Clock (8XMODE Reg.) Receive Data Shift Register (RSR) 64 bytes by 11- bit wide FIFO Receive Data Receive Data Byte ...

Page 32

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by: ...

Page 33

REV. 1.2.2 5.5 Infrared Mode Each UART in the D154 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 4 UART channels to start up in ...

Page 34

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 5.6 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART ...

Page 35

REV. 1.2.2 Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with the EXAR enhanced feature registers located on next 8 addresses locations. Addresses 0x080 to 0x093 comprise the ...

Page 36

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART T 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit-7 0 ...

Page 37

REV. 1.2.2 T 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE XCHAR XOFF1 W Bit-7 ...

Page 38

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed ...

Page 39

REV. 1.2.2 Interrupt Generation: • LSR is by any of the LSR bits and 4. • RXRDY trigger level. • RXRDY Time-out is by the a 4-char plus 12 bits delay timer if ...

Page 40

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART ISR[4]: Xoff/Xon or Special Character Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of ...

Page 41

REV. 1.2.2 FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receiv- er ...

Page 42

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 5.8.7 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and ...

Page 43

REV. 1.2.2 LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW ...

Page 44

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART MCR[5]: Xon-Any Enable • Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default). • Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, ...

Page 45

REV. 1.2.2 LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In addition, this bit causes the UART ...

Page 46

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART MSR[5]: DSR Input Status This input may be used for auto DTR/DSR flow control function, see (RTS/CTS or DTR/DSR) Flow Control Operation” on page 31 flow control is not used, this ...

Page 47

REV. 1.2.2 5.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a ...

Page 48

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART T 18 ABLE ELECTABLE FCTR B -3 FCTR ...

Page 49

REV. 1.2.2 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR ...

Page 50

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/ DTR is selected, an ...

Page 51

REV. 1.2.2 REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-3:0] RTS#[ch-3:0] DTR#[ch-3:0] EECK EECS EEDI UNIVERSAL (3.3V AND 5V) PCI ...

Page 52

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 6.0 PROGRAMMING EXAMPLES 6 NLOADING ECEIVE ATA It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any ...

Page 53

REV. 1.2.2 ABSOLUTE MAXIMUM RATINGS Power Supply Range (VCC) Voltage at any PCI Bus Pin Voltage at any non-PCI Bus Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 5V PCI ...

Page 54

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART AC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5-5.5V TA (-40 to +85 C for industrial grade package). S ...

Page 55

REV. 1.2.2 DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V TA (-40 to +85 C for industrial grade package YMBOL ARAMETER V Input High ...

Page 56

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V TA (-40 to +85 C for industrial grade package). S ...

Page 57

REV. 1.2 IGURE IMING OR XTERNAL 2V External Clock 0.8V UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART C I XTAL1 P LOCK NPUT ECLK T ECH 57 XR17D154 T ECL ...

Page 58

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART F 20. PCI B C IGURE US ONFIGURATION CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# ...

Page 59

REV. 1.2 IGURE EVICE ONFIGURATION AND CLK Host 1 2 FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address PAR Parity Host Target ...

Page 60

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART F 22 IGURE EVICE ONFIGURATION REGISTERS TION CLK Host FRAME# Host Data AD[31:0] Address DWORD Host Target Bus C/BE[3:0]# Byte Enable# = DWORD CMD Host IRDY# ...

Page 61

REV. 1.2 IGURE EVICE ONFIGURATION CLK Host 1 FRAME# Host AD[31:0] AD Host Target C/BE[3:0]# Bus Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# Target PAR AD Host Target PERR# Target SERR# ...

Page 62

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART F 24. 5V PCI B C (DC IGURE US LOCK 4 nSec (max) CLK Tval (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Bused Signal Input 33MH ...

Page 63

REV. 1.2.2 F 25. 3.3V PCI B C (DC IGURE US LOCK 1.44 ns (max) CLK Tvalid (2-11 ns) Bused Signal Output Delay Ton (2 ns min) Tri-State Output Bused Signal Input UNIVERSAL (3.3V AND 5V) PCI BUS QUAD ...

Page 64

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART F 26 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 27 IGURE ECEIVE ATA EADY START BIT ...

Page 65

REV. 1.2.2 PACKAGE DIMENSIONS 108 109 144 1 A Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL α UNIVERSAL (3.3V AND 5V) ...

Page 66

... August 2005 Rev 1.2.2 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...

Page 67

REV. 1.2.2 GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS FEATURES......................................................................................................................... ............................................................................................................................................................. 1 IGURE LOCK IAGRAM ................................................................................................................................ 2 ORDERING INFORMATION .................................................................................................................................................. 2 IGURE THE EVICE PIN DESCRIPTIONS ...

Page 68

XR17D154 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 5.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 28 5.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. IGURE RANSMITTER PERATION IN NON 5.2.3 TRANSMITTER OPERATION IN FIFO MODE ...

Page 69

REV. 1.2 IGURE EVICE ONFIGURATION REGISTERS F 23 IGURE EVICE ONFIGURATION F 24. 5V PCI B C (DC IGURE US LOCK F 25. 3.3V PCI B C (DC IGURE US LOCK F 26. ...

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