S2004TB Applied Micro Circuits Corporation, S2004TB Datasheet

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S2004TB

Manufacturer Part Number
S2004TB
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of S2004TB

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.47V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Lead Free Status / RoHS Status
Not Compliant

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FEATURES
APPLICATIONS
Figure 1. Typical Quad Gigabit Ethernet Application
DEVICE
SPECIFICATION
October 10, 2000 / Revision D
QUAD SERIAL BACKPLANE DEVICE
QUAD SERIAL BACKPLANE DEVICE
• Broad operating rate range (.98 - 1.3 GHz)
• Quad Transmitter with phase-locked loop (PLL)
• Quad Receiver PLL provides clock and data
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for
• 32-bit parallel TTL interface with internal series
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.5 W power dissipation
• Compact 23mm x 23mm 208 TBGA package
• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
clock synthesis from low speed reference
recovery
four separate parallel 8-bit channels
terminated outputs
signals
INTERFACE
ETHERNET
GIGABIT
QUAD
GE INTERFACE
S2204
GENERAL DESCRIPTION
The S2004 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides four
separate transceivers which can be operated indi-
vidually or locked together for an aggregate data ca-
pacity of >4 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip quad
receive PLL is used for clock recovery and data re-
timing on the four independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a 3.3V power supply and dissi-
pates 2.5 watts.
Figure 1 shows the S2004 and S2204 in a Gigabit
Ethernet application. Figure 2 combines the S2004
with a crosspoint switch to demonstrate a serial
backplane application. Figure 3 is the input/output
diagram. Figures 4 and 5 show the transmit and
receive block diagrams, respectively.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
SERIAL BP DRIVER
S2004
TO SERIAL BACKPLANE
S2004
S2004
®
1

Related parts for S2004TB

S2004TB Summary of contents

Page 1

DEVICE SPECIFICATION QUAD SERIAL BACKPLANE DEVICE QUAD SERIAL BACKPLANE DEVICE FEATURES • Broad operating rate range (.98 - 1.3 GHz) - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - 1/2 Rate Operation • Quad Transmitter with ...

Page 2

S2004 Figure 2. Typical Backplane Application MAC (ASIC) MAC ATM (ASIC) Fibre S2004 Channel Ethernet MAC Etc. (ASIC) MAC (ASIC) MAC (ASIC) ATM MAC Fibre (ASIC) Channel S2004 Ethernet MAC Etc. (ASIC) MAC (ASIC) 2 QUAD SERIAL BACKPLANE DEVICE Crosspoint ...

Page 3

QUAD SERIAL BACKPLANE DEVICE Figure 3. S2004 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO SYNC DINA[0:7] 10 DNA, KGENA TCLKA DINB[0:7] 10 DNB, KGENB TCLKB DINC[0:7] 10 DNC, KGENC TCLKC DIND[0:7] 10 DND, KGEND TCLKD ERRA DOUTA[0:7] 10 EOFA, ...

Page 4

S2004 Figure 4. Transmitter Block Diagram RATE REFCLK CLKSEL CH_LOCK TMODE 8 DINA[0:7] FIFO SYNC (input) DNA KGENA TCLKA 8 DINB[0:7] FIFO (input) DNB KGENB TCLKB 8 DINC[0:7] FIFO (input) DNC KGENC ...

Page 5

QUAD SERIAL BACKPLANE DEVICE Figure 5. Receiver Block Diagram CMODE RATE REFCLK EOFA KFLAGA FIFO (output) ERRA 8 Q DOUTA[0:7] 2 RCAP/N EOFB KFLAGB FIFO (output) ERRB 8 DOUTB[0:7] 2 RCBP/N EOFC KFLAGC FIFO (output) ERRC 8 DOUTC[0:7] 2 RCCP/N ...

Page 6

S2004 TRANSMITTER DESCRIPTION The transmitter section of the S2004 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Four channels are provided with a variety of options regarding input clocking and loopback. ...

Page 7

QUAD SERIAL BACKPLANE DEVICE Figure 6. DINx Data Clocking with TCLK TCLKO DINx[0:7] TCLKx MAC ASIC The S2004 also supports the traditional REFCLK (TBC) clocking found in many Fibre Channel and Gigabit Ethernet applications and is illustrated in Fig- ure ...

Page 8

S2004 In order to provide interface compatibility to non- AMCC serial backplane transceivers, the S2004 can also generate a unique sync character consisting of 16 consecutive K28.5 characters. This event is initi- ated by the simultaneous assertion of SYNC and ...

Page 9

QUAD SERIAL BACKPLANE DEVICE Table 3. K Character Generation (DNx = 1 KGENx =1 SYNC = ...

Page 10

S2004 RECEIVER DESCRIPTION Each receiver channel is designed to implement a Serial Backplane receiver function through the physi- cal layer. A block diagram showing the basic func- tion is provided in Figure 5. Whenever a signal is present, the receiver ...

Page 11

QUAD SERIAL BACKPLANE DEVICE Serial to Parallel Conversion Once bit synchronization has been attained by the S2004 CRU, the S2004 must synchronize to the 10 bit word boundary. Word synchronization in the S2004 is accomplished by detecting and aligning to ...

Page 12

S2004 Figure 8. Channel Lock State Machine All four channels in Re-Sync with valid data within deskew window RE-SYNC Figure 9. Channel Lock Synchronization Timing (Internal) RESYNC A (Internal) RESYNC B (Internal) RESYNC C (Internal) RESYNC D (internal) deskewed RESYNC ...

Page 13

QUAD SERIAL BACKPLANE DEVICE Table 7. Error and Status Reporting ...

Page 14

S2004 CHANNEL LOCKING/RE-LOCKING PROCEDURE The Channel locking/relocking procedures are sum- marized below. Following these procedures will in- sure proper CHANNEL LOCK operation of the device. When powered up, the S2004 will lock to the received data within approximately 2500 bit ...

Page 15

QUAD SERIAL BACKPLANE DEVICE When TCLKA is the output clock source, REFCLK and TCLKA must equal the parallel word rate (CLKSEL = Low). Additionally, the recovered clocks and the clock input on TCLKA must be frequency locked in order to ...

Page 16

S2004 OTHER OPERATING MODES Operating Frequency Range The S2004 is designed to operate at serial baud rates of .98 GHz to 1.3 GHz (800 Mbps to 1040 Mbps user data rate). The part is specified at Fibre Channel (1062 MHz) ...

Page 17

QUAD SERIAL BACKPLANE DEVICE The following table provides a list of the pins that are JTAG tested. Each port has a boundary scan register (BSR), unless otherwise noted. The following features are described: the JTAG mode of each register (input, ...

Page 18

S2004 Table 9. JTAG Pin Assignments (Continued ...

Page 19

QUAD SERIAL BACKPLANE DEVICE Table 10. Transmitter Input Pin Assignment and Descriptions ...

Page 20

S2004 Table 10. Transmitter Signal Descriptions (Continued ...

Page 21

QUAD SERIAL BACKPLANE DEVICE Table 11. Transmitter Output Signals ...

Page 22

S2004 Table 13. Receiver Output Pin Assignment and Descriptions ...

Page 23

QUAD SERIAL BACKPLANE DEVICE Table 13. Receiver Output Pin Assignment and Descriptions (Continued ...

Page 24

S2004 Table 14. Receiver Input Pin Assignment and Descriptions ...

Page 25

QUAD SERIAL BACKPLANE DEVICE Table 16. Power and Ground Signals (Continued ...

Page 26

S2004 Table 17. JTAG Test Signals ...

Page 27

QUAD SERIAL BACKPLANE DEVICE Figure 12. S2004 Pinout (Bottom View ...

Page 28

S2004 Figure 13. S2004 Pinout (Top View ...

Page 29

QUAD SERIAL BACKPLANE DEVICE Figure 14. Compact 23mm x 23mm 208 TBGA Package Thermal Management October 10, 2000 / Revision ...

Page 30

S2004 Figure 15. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 0) REFCLK DINx[0:7], DNx, KGENx, SYNC SERIAL DATA OUT Table 18. S2004 Transmitter Timing (Normal or Channel Lock Mode, TMODE = ...

Page 31

QUAD SERIAL BACKPLANE DEVICE Table 20. S2004 Receiver Timing (Full and Half Clock Mode ...

Page 32

S2004 Figure 17. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Figure 18. Receiver Timing (Half Clock Mode, CMODE = 0, TMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, ...

Page 33

QUAD SERIAL BACKPLANE DEVICE Figure 20. TCLKO Timing REFCLK TCLKO Table 22. S2004 Transmitter (TCLKO Timing ...

Page 34

S2004 Table 23. Absolute Maximum Ratings ...

Page 35

QUAD SERIAL BACKPLANE DEVICE Table 26. Serial Data Timing, Transmit Outputs ...

Page 36

S2004 OUTPUT LOAD The S2004 serial outputs do not require output pulldown resistors. ACQUISITION TIME With the input eye diagram shown in Figure 26, the S2004 will recover data with a 1E-9 BER within the time specified ...

Page 37

QUAD SERIAL BACKPLANE DEVICE Figure 27. Loop Filter Capacitor Connections October 10, 2000 / Revision D 270 CAP1 22 nf CAP2 270 S2004 S2004 37 ...

Page 38

... Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...

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