ISP1507CBS STEricsson, ISP1507CBS Datasheet
ISP1507CBS
Specifications of ISP1507CBS
Related parts for ISP1507CBS
ISP1507CBS Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1507C; ISP1507D ULPI Hi-Speed Universal Serial Bus host and peripheral transceiver Rev. 01 — 28 May 2008 1. General description The ISP1507 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial ...
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... N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1507CBS) and 26 MHz (ISP1507DBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1507CBS 507C 19.2 MHz [1] ISP1507DBS 507D 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1507C_ISP1507D_1 Product data sheet ISP1507C; ISP1507D ...
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NXP Semiconductors 5. Block diagram 21 CLOCK 15 STP 14 DIR 16 ULPI NXT INTERFACE 20, 8 22, 24 DATA [7:0] 12 RESET_N/ PSW_N 10 XTAL1 11 XTAL2 CC(I/O) 9 REG3V3 13 REG1V8 ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Type DATA1 1 I/O DATA0 2 I CC(I/O) RREF AI/O V ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type RESET_N/PSW_N 12 I/O REG1V8 13 P DIR 14 O STP 15 I NXT 16 O DATA7 17 I/O DATA6 18 I/O DATA5 19 I/O DATA4 20 I/O CLOCK 21 ...
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NXP Semiconductors 7. Functional description 7.1 ULPI controller The ISP1507 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI controller provides ...
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NXP Semiconductors • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode • bus terminations on DP and DM for host and OTG modes For details on controlling resistor settings, see ...
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NXP Semiconductors While it is possible for the external 5 V supply to use the ISP1507 internal A_VBUS_VLD comparator, typical 5 V supplies must provide their own power fault indicator that can be connected as an input to the ISP1507 ...
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NXP Semiconductors 7.10.2 V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.10.3 RREF Resistor reference analog I/O pin. A ...
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NXP Semiconductors 7.10.7 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1507 internal digital and analog circuits, and must not be used to power external circuits. For correct operation of the regulator recommended ...
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NXP Semiconductors 7.10.10 DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1507 holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1507 listens for data ...
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NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1507 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one ...
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NXP Semiconductors Table 3. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1507 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that ...
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NXP Semiconductors Table 4. Signal mapping during low-power mode Signal Maps to Direction Reserved DATA2 O INT DATA3 O Reserved DATA[7:4] O 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and ...
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NXP Semiconductors Table 6. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than ...
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NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Host low-speed 10b suspend Host low-speed 10b resume Host Test J or Test K 00b Peripheral settings Peripheral chirp 00b Peripheral 00b ...
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NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1507. 9.1 ULPI references The ISP1507 provides a 12-pin ULPI to communicate with the link highly recommended that you read UTMI+ Low Pin Interface ...
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NXP Semiconductors If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 4. ...
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NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1507. The ISP1507 regulator starts to turn on. CC ...
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NXP Semiconductors The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1507 will ...
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NXP Semiconductors The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD. 9.5 TXCMD and RXCMD Commands between the ISP1507 and the link ...
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NXP Semiconductors Table 9. RXCMD byte format DATA Name Description and value LINESTATE LINESTATE signals: For a definition of LINESTATE, see DATA0 — LINESTATE[0] DATA1 — LINESTATE[ state Encoded V BUS 5 to ...
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NXP Semiconductors Table 10. LINESTATE[1:0] encoding for upstream facing ports: peripherals [1] DP_PULLDOWN = 0. Mode Full-speed XCVRSELECT[1:0] 01, 11 TERMSELECT 1 LINESTATE[1:0] 00 SE0 01 FS-J 10 FS-K 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. ...
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NXP Semiconductors V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 7. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the ...
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NXP Semiconductors Standard USB peripheral controllers: when V start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END thresholds is not needed for standard peripherals. OTG devices: that supplies less than 100 pin. The internal ...
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NXP Semiconductors enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers, respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the link with the updated value. 9.6 Register read and ...
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NXP Semiconductors 2. High-speed detection handshake (chirp) a. Peripheral chirp: After detecting SE0 for no less than 2 the peripheral is capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and OPMODE[1:0] = 10b (chirp). The peripheral immediately ...
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NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR ...
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NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD ...
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NXP Semiconductors Table 16. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK D ...
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NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 12. High-speed receive-to-transmit packet timing 9.9 ...
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NXP Semiconductors CLOCK DATA[7: Fig 13. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed and low-speed host-initiated suspend and resume Figure 14 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note ...
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NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 14. Full-speed suspend and ...
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NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1507 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN ...
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NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM ...
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NXP Semiconductors 9.10.3 Remote wake-up The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of ...
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NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 16. Remote ...
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NXP Semiconductors PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the ...
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NXP Semiconductors 9.12.1 OTG comparators The ISP1507 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V B_SESS_VLD are communicated to the link by RXCMDs as described in comparators ...
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NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 18. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 ...
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NXP Semiconductors 9.14 Aborting transfers The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 . 9.15 Avoiding contention on the ULPI data bus Because the ULPI ...
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NXP Semiconductors 10. Register map Table 17. Immediate register set overview Field name VENDOR_ID_LOW VENDOR_ID_HIGH PRODUCT_ID_LOW PRODUCT_ID_HIGH FUNC_CTRL INTF_CTRL OTG_CTRL USB_INTR_EN_R_E USB_INTR_EN_F_E USB_INTR_STAT USB_INTR_L DEBUG SCRATCH Reserved (do not use) Access extended register set Vendor-specific registers PWR_CTRL [1] Read (R): ...
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NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 VENDOR_ID_LOW register Table 19 Table 19. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Bit Symbol Access Value VENDOR_ID_ ...
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NXP Semiconductors Table 24. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. ...
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NXP Semiconductors Table 25. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit allocation Bit 7 Symbol INTF_ IND_PASS PROT_DIS THRU Reset 0 Access R/W/S/C R/W/S/C Table 26. ...
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NXP Semiconductors 10.1.4 OTG_CTRL register This register controls various OTG functions of the ISP1507. The bit allocation of the OTG_CTRL register is given in Table 27. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah, ...
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NXP Semiconductors Table 29. USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation Bit 7 Symbol Reset 0 Access R/W/S/C R/W/S/C Table 30. USB_INTR_EN_R_E ...
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NXP Semiconductors 10.1.7 USB_INTR_STAT register This register (see Table 33. USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation Bit 7 Symbol Reset X Access R Table 34. USB_INTR_STAT - USB Interrupt Status register (address R = ...
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NXP Semiconductors 10.1.9 DEBUG register The bit allocation of the DEBUG register is given in current value of signals useful for debugging. Table 37. DEBUG - Debug register (address R = 15h) bit allocation Bit 7 Symbol Reset 0 Access ...
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NXP Semiconductors Table 41. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic ...
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NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from V ...
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NXP Semiconductors 12. Limiting values Table 42. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I ...
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NXP Semiconductors 14. Static characteristics Table 44. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 45. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N CC(I/O) Typical values are 3 ...
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NXP Semiconductors Table 47. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 48. Static characteristics CC(I/O) Typical values are 3 Symbol Parameter V A-device V A_VBUS_VLD ...
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... CC(I/O) amb Conditions 4 capacitor each on pins REG1V8 and REG3V3 ISP1507CBS ISP1507DBS ISP1507CBS ISP1507DBS applicable only when clock is applied on pin XTAL1 only for square wave input only for square wave input only for square wave input measured from power good or assertion of pin STP ...
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NXP Semiconductors Table 52. Dynamic characteristics: digital I/O pins +85 C; unless otherwise specified. CC amb Symbol Parameter t DATA output delay with respect d(DATA) to the rising ...
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NXP Semiconductors Table 53. Dynamic characteristics: analog I/O pins (DP CC(I/O) Symbol Parameter t transition time: fall time LF t rise and fall ...
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NXP Semiconductors HSR Fig 21. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential ...
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NXP Semiconductors 16. Application information Table 54. Recommended bill of materials [1] Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG D ...
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... STANDARD-A RECEPTACLE SHIELD 5 C VBUS A1 SHIELD 6 IP4359CX4/LF B1 SHIELD 7 SHIELD 8 (1) Frequency is version dependent: ISP1507CBS: 19.2 MHz; ISP1507DBS: 26 MHz. Fig 26. Using the ISP1507 with a USB host controller; external 5 V source with built-in FAULT and external crystal CC(I/O) C bypass DATA1 1 DATA0 2 V CC(I/O) 3 ...
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... STANDARD-B RECEPTACLE A1 A2 SHIELD 5 IP4359CX4/LF SHIELD ESD SHIELD 7 SHIELD C VBUS 8 f i(XTAL1) (1) Frequency is version dependent: ISP1507CBS: 19.2 MHz; ISP1507DBS: 26 MHz. Fig 27. Using the ISP1507 with a peripheral controller; external square wave input on pin XTAL1 V CC(I/ bypass DATA1 1 24 DATA0 CC(I/ RREF RREF ...
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NXP Semiconductors 17. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area ...
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NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction ...
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NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 57. Acronym ASIC ATX CD-RW EOP ESD ESR FS ...
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NXP Semiconductors Table 57. Acronym PID PLD PLL POR RoHS RXCMD SE0 SOF SRP STB SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification ...
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NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
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NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 10.1.3 INTF_CTRL register . . . . . . . . . . . . . . . . . . . . 45 10.1.4 OTG_CTRL register . . . . . . . . . . . ...