ISP1507CBSUM STEricsson, ISP1507CBSUM Datasheet
ISP1507CBSUM
Specifications of ISP1507CBSUM
Related parts for ISP1507CBSUM
ISP1507CBSUM Summary of contents
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ISP1507C; ISP1507D ULPI Hi-Speed USB host and peripheral transceiver Rev. 04 — 20 May 2010 1. General description The ISP1507 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification ...
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Highly optimized ULPI compliant 60 MHz, 12-bit interface between the core and the transceiver Supports 60 MHz output clock configuration Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1507CBS) and 26 MHz (ISP1507DBS) Fully programmable ULPI-compliant ...
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... Ordering information Table 1. Ordering information Commercial Marking Crystal or clock product code frequency [1] ISP1507CBSUM 507C 19.2 MHz [1] ISP1507DBSUM 507D 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. CD00222690 Product data sheet ISP1507C; ISP1507D ULPI HS USB host and peripheral transceiver ...
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Block diagram 21 CLOCK 15 STP 14 DIR 16 ULPI NXT INTERFACE 20, 8 22, 24 DATA [7:0] 12 RESET_N/ PSW_N 10 XTAL1 11 XTAL2 CC(I/O) 9 REG3V3 13 REG1V8 7 V ...
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Pinning information 6.1 Pinning Fig 2. Pin configuration HVQFN24; top view 6.2 Pin description Table 2. Pin description [1][2] [3] Symbol Pin Type DATA1 1 I/O DATA0 2 I CC(I/O) RREF 4 AI AI/O ...
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Table 2. Pin description …continued [1][2] [3] Symbol Pin Type RESET_N/PSW_N 12 I/O REG1V8 13 P DIR 14 O STP 15 I NXT 16 O DATA7 17 I/O DATA6 18 I/O DATA5 19 I/O DATA4 20 I/O CLOCK 21 O ...
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Functional description 7.1 ULPI controller The ISP1507 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to the USB link. The ULPI controller provides the following functions: ...
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High-speed disconnect detector 45 Ω high-speed bus terminations on DP and DM for peripheral and host modes • • 1.5 kΩ pull-up resistor on DP for full-speed peripheral mode • 15 kΩ bus terminations on DP and DM for ...
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While it is possible for the external 5 V supply to use the ISP1507 internal A_VBUS_VLD comparator, typical 5 V supplies must provide their own power fault indicator that can be connected as an input to the ISP1507 FAULT pin. ...
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V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.10.3 RREF Resistor reference analog I/O pin. A resistor, R ...
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REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1507 internal digital and analog circuits, and must not be used to power external circuits. For correct operation of the regulator recommended that you ...
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DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1507 holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1507 listens for data from the ...
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Modes of operation 8.1 ULPI modes The ISP1507 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will ...
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Table 3. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1507 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in ...
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Table 4. Signal mapping during low-power mode Signal Maps to Direction Reserved DATA2 O INT DATA3 O Reserved DATA[7:4] O 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed ...
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Table 6. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical ...
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Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] Host low-speed 10b 1b suspend Host low-speed 10b 1b resume Host Test J or Test K 00b 0b Peripheral settings Peripheral chirp ...
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Protocol description The following subsections describe the protocol for using the ISP1507. 9.1 ULPI references The ISP1507 provides a 12-pin ULPI to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) Specification ...
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If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 4. The recommended ...
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CC(I/O) REG1V8 t REGUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1507. The ISP1507 regulator starts to turn on. CC CC(I/O) t2 ...
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The interface protect feature prevents unwanted activity of the ISP1507 whenever the ULPI is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1507. The interface protect feature can be disabled by ...
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The ISP1507 supports external V indicator signal. The indicator signal must be connected to the V the ISP1507 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit in the OTG_CTRL register (see INTF_CTRL register (see The ...
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An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt condition is removed before exiting. Table 9. RXCMD byte format DATA Name Description and value LINESTATE LINESTATE signals: For a definition ...
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Table 10. LINESTATE[1:0] encoding for upstream facing ports: peripherals [1] DP_PULLDOWN = 0. Mode Full-speed XCVRSELECT[1:0] 01, 11 TERMSELECT 1 LINESTATE[1:0] 00 SE0 01 FS-J 10 FS-K 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. Table 11. ...
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V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 7. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB_INTR_EN_R_E and ...
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OTG devices: that supplies less than 100 pin. The internal A_VBUS_VLD comparator can be used. If the OTG A-device provides more than 100 USB host controllers” on page 25 detect when an OTG B-device ...
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Register read and write operations Figure 8 shows register read and write sequences. The ISP1507 supports immediate addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ...
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High-speed detection handshake (chirp) a. Peripheral chirp: After detecting SE0 for no less than 2.5 μs, if the peripheral is capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this ...
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USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT ...
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USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD DIR STP NXT ...
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Allowed link decision time The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in values given in packet sequences and timing are shown in UTMI+ Low ...
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DP or DATA DM CLOCK D D N−1 N DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 11. High-speed transmit-to-transmit packet timing DP or EOP DATA DM CLOCK N−4 N−2 DATA ...
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ISP1507 operates just as in full-speed mode, and sends all data with the full-speed rise time and fall time. Whenever the link transmits a USB packet in preamble mode, the ISP1507 will automatically send a preamble header ...
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Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake ...
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DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 14. Full-speed suspend and resume ...
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The sequence of events related to a host and a peripheral, both with ISP1507 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN ...
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HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP ...
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Remote wake-up The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols ...
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LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 16. Remote wake-up from ...
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PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must ...
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OTG comparators The ISP1507 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V B_SESS_VLD are communicated to the link by RXCMDs as described in comparators is described ...
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SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 18. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 19. ...
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Aborting transfers The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 9.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is ...
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Register map Table 17. Immediate register set overview Field name VENDOR_ID_LOW VENDOR_ID_HIGH PRODUCT_ID_LOW PRODUCT_ID_HIGH FUNC_CTRL INTF_CTRL OTG_CTRL USB_INTR_EN_R_E USB_INTR_EN_F_E USB_INTR_STAT USB_INTR_L DEBUG SCRATCH Reserved (do not use) Access extended register set Vendor-specific registers PWR_CTRL [1] Read (R): A register ...
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Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 VENDOR_ID_LOW register Table 19 shows the bit description of the register. Table 19. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Legend: * reset ...
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Table 24. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the ...
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Table 26. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1507 to protect ...
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Table 27. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 6 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 0 Access R/W/S/C R/W/S/C Table 28. ...
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Table 29. USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation Bit 7 6 Symbol Reset 0 0 Access R/W/S/C R/W/S/C Table 30. USB_INTR_EN_R_E ...
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USB_INTR_STAT register This register (see Table 33. USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation Bit 7 6 Symbol Reset X X Access R R Table 34. USB_INTR_STAT - USB Interrupt Status register (address R ...
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DEBUG register The bit allocation of the DEBUG register is given in current value of signals useful for debugging. Table 37. DEBUG - Debug register (address R = 15h) bit allocation Bit 7 6 Symbol Reset 0 0 Access ...
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Table 41. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic 1 to ...
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ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, V minimum of ±4 kV ESD protection. Capacitors 0.1 μF and 1 μF must be connected in parallel from V Remark: Capacitors ...
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Limiting values Table 42. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current ...
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Static characteristics Table 44. Static characteristics: supply pins CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V ...
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Table 45. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N CC(I/O) Typical values are 3 CC(I/O) ...
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Table 47. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Resistance ...
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Table 48. Static characteristics CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V A-device V valid voltage ...
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Dynamic characteristics Table 51. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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Table 52. Dynamic characteristics: digital I/O pins − ° 3 3 +85 CC amb Symbol Parameter 1.95 V CC(I/O) t DATA set-up time with respect ...
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Table 53. Dynamic characteristics: analog I/O pins (DP CC(I/O) Symbol Parameter V output signal crossover CRS voltage Low-speed driver t transition time: rise ...
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HSR Fig 21. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL ...
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Application information Table 54. Recommended list of materials [1] Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG R recommended; for ...
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V IN FAULT R pullup V BUS SWITCH ON OUT V BUS 1 D− GND USB 4 STANDARD-A RECEPTACLE SHIELD 5 C VBUS SHIELD 6 SHIELD 7 SHIELD ...
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R VBUS V BUS USB GND 4 STANDARD-B RECEPTACLE SHIELD 5 SHIELD 6 SHIELD 7 SHIELD C VBUS 8 f i(XTAL1) (1) Frequency is version dependent: ...
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Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS ...
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Abbreviations Table 55. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS MO NRZI OTG PCB PDA PHY PID PLD PLL POR RoHS RXCMD SE0 SOF SRP STB SYNC TTL TXCMD USB USB-IF ULPI ...
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References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN24; top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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INTF_CTRL register . . . . . . . . . . . . . . . . . . . . 46 10.1.4 OTG_CTRL register . . . . . . . . . . . . . ...
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... ULPI HS USB host and peripheral transceiver Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 04 — 20 May 2010 ISP1507C; ISP1507D © ST-ERICSSON 2010. All rights reserved. ...