ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet
ISP1507B1HNTM
Specifications of ISP1507B1HNTM
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ISP1507B1HNTM Summary of contents
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ULPI Hi-Speed USB OTG transceiver Rev. 03 — 26 July 2010 1. General description The ISP1507A1; ISP1507B1 (ISP1507x1 Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement ...
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Data line and V Integrated V Integrated cable (ID) detector Highly optimized ULPI-compliant 60 MHz, 12-bit interface between the core and the transceiver Supports 60 MHz output clock configuration Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 ...
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... ISP1507A1HNTM 19.2 MHz ISP1507B1HNTM 26 MHz 5. Marking Table 2. Commercial product code ISP1507A1HNTM ISP1507B1HNTM [1] The package marking is the first and second lines of text on the IC package, and can be used for IC identification. CD00269905 Product data sheet ISP1507A1; ISP1507B1 Package description HVQFN32; 32 terminals; body 5 × 5 × 0.85 mm HVQFN32 ...
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Block diagram 27 CLOCK 26, 8 28, 31, 32 DATA [7:0] ULPI INTERFACE 19 DIR 20 STP 21 NXT 29 CHIP_SELECT_N 17 RESET_N GLOBAL CLOCKS 15 XTAL1 16 XTAL2 2, 22, 30 interface voltage V CC(I/O) ...
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Pinning information 7.1 Pinning Fig 2. Pin configuration HVQFN32 7.2 Pin description Table 3. [1][2] Symbol DATA0 V CC(I/O) RREF DM DP FAULT ID GND n.c. n.c. CD00269905 Product data sheet ISP1507A1; ISP1507B1 terminal 1 index area DATA0 1 ...
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Table 3. [1][2] Symbol V CC PSW_N V BUS REG3V3 XTAL1 XTAL2 RESET_N REG1V8 DIR STP NXT V CC(I/O) DATA7 DATA6 DATA5 DATA4 CLOCK DATA3 CHIP_SELECT_N 29 V CC(I/O) CD00269905 Product data sheet ISP1507A1; ISP1507B1 Pin description …continued [3] Pin ...
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Table 3. [1][2] Symbol DATA2 DATA1 GND [1] Symbol names ending with underscore N, for example, NAME_N, indicate active-LOW signals. [2] For details on external components required on each pin, see list of materials and application diagrams in Section [3] ...
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Functional description 8.1 ULPI interface controller The ISP1507x1 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to the USB link. The ULPI interface controller provides the ...
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Squelch circuit to detect high-speed bus activity • High-speed disconnect detector • 45 Ω high-speed bus terminations on DP and DM for peripheral and host modes • 1.5 kΩ pull-up resistor on DP for full-speed peripheral mode • 15 ...
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ID detector The ID detector detects which end of the micro-USB cable is plugged in. The detector must first be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1507x1 senses a value on ID that ...
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Power-On Reset (POR) The ISP1507x1 has an internal power-on reset circuit that resets all internal logic on power-up. The ULPI interface is also reset on power-up. Remark: When CLOCK starts toggling after power-up, the USB link must issue a ...
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Set the USE_EXT_VBUS_IND register bit to logic 1. • Set the polarity of the external fault signal using the IND_COMPL register bit. • Set the IND_PASSTHRU register bit to logic 1. If the FAULT pin is not used, it ...
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XTAL1 and XTAL2 XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the XTAL1 pin depends on the ISP1507x1 product version. If the link requires a 60 MHz clock from the ISP1507x1, then ...
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NXT ULPI next data output pin. The ISP1507x1 holds NXT at LOW, by default. When DIR is LOW and the link is sending data to the ISP1507x1, NXT will be asserted to notify the link to provide the next ...
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Modes of operation 9.1 ULPI modes The ISP1507x1 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will ...
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Table 4. Signal name DIR STP NXT 9.1.2 Low-power mode When the USB is idle, the link can place the ISP1507x1 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in ...
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Table 5. Signal mapping during low-power mode Signal Maps to Direction Reserved DATA2 O INT DATA3 O Reserved DATA[7: output. 9.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to ...
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Table 7. Signal mapping for 3-pin serial mode Signal Maps to Direction TX_ENABLE DATA0 I DAT DATA1 I/O SE0 DATA2 I/O INT DATA3 O Reserved DATA[7: input output; I/O = input/output. 9.2 USB and ...
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Table 8. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] Host low-speed 10b 1b suspend Host low-speed 10b 1b resume Host Test J or Test K 00b 0b Peripheral settings Peripheral chirp ...
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Protocol description The following subsections describe the protocol for using the ISP1507x1. 10.1 ULPI references The ISP1507x1 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) ...
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If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507x1 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 4. The recommended ...
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CC(I/O) REG1V8 t REGUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1507x1. The ISP1507x1 regulator starts to turn on. CC CC(I/O) t2 ...
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The interface protect feature prevents unwanted activity of the ISP1507x1 whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1507x1. The interface protect feature can be disabled ...
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The ULPI controller is forced into an idle state and any ULPI command is ignored. entering 3-state mode CLOCK CHIP_ SELECT_N DATA[7:0] DIR NXT STP Fig 6. Entering and exiting 3-state in normal mode CLOCK CHIP_ SELECT_N DATA[7:0] TXCMD ...
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V power and fault detection BUS 10.4.1 Driving The ISP1507x1 also supports external 5 V supplies. The ISP1507x1 can control the external supply using the active-LOW PSW_N open-drain output pin. To enable the external supply ...
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Table 10. TXCMD byte format …continued Command Command code Command payload type name DATA[7:6] DATA[5:0] Register 10b 10 1111b write XX XXXXb Register read 11b 10 1111b XX XXXXb 10.5.2 RXCMD The ISP1507x1 communicates status information to the link by ...
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CLOCK turnaround DATA [ 7:0 ] DIR STP NXT Fig 8. Single and back-to-back RXCMDs from the ISP1507x1 to the link 10.5.2.1 Linestate encoding LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1507x1 detects a change in ...
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Table 13. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. ...
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USE_EXT_VBUS_IND, IND_PASSTHRU Fig 9. RXCMD A_VBUS_VLD indicator source 10.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers. The link ...
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OTG devices: provide a minimum then there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 ...
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Register read and write operations Figure 10 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1507x1 unexpectedly asserts DIR during the operation. When a register ...
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T up its clock within 5.6 ms, leaving 200 μs for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10% slow clock). ...
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USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT ...
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USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD CLOCK DATA[7:0] TXCMD DIR STP NXT Fig 12. Example ...
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Allowed link decision time The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in values given in packet sequences and timing are shown in UTMI+ Low ...
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DP or DATA DM CLOCK D D N−1 N DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 13. High-speed transmit-to-transmit packet timing DP or EOP DATA DM CLOCK N−4 N−2 DATA ...
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ISP1507x1 operates just as in full-speed mode, and sends all data with the full-speed rise time and fall time. Whenever the link transmits a USB packet in preamble mode, the ISP1507x1 will automatically send a preamble header ...
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Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake ...
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DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 16. Full-speed suspend and resume ...
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The sequence of events related to a host and a peripheral, both with ISP1507x1 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN ...
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HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP ...
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Remote wake-up The ISP1507x1 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols ...
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LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 18. Remote wake-up from ...
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PHY will not transmit any EOP. The ISP1507x1 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must ...
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OTG comparators The ISP1507x1 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V B_SESS_VLD are communicated to the link by RXCMDs as described in comparators is described ...
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SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 20. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 21. ...
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Aborting transfers The ISP1507x1 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 10.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is ...
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Register map Table 19. Immediate register set overview Field name Size (bit) VENDOR_ID_LOW 8 VENDOR_ID_HIGH 8 PRODUCT_ID_LOW 8 PRODUCT_ID_HIGH 8 FUNC_CTRL 8 INTF_CTRL 8 OTG_CTRL 8 USB_INTR_EN_R_E 8 USB_INTR_EN_F_E 8 USB_INTR_STAT 8 USB_INTR_L 8 DEBUG 8 SCRATCH 8 Reserved ...
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Immediate register set 11.1.1 Vendor ID and product ID registers 11.1.1.1 VENDOR_ID_LOW register Table 21 shows the bit description of the register. Table 21. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Legend: * reset ...
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Table 26. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active-LOW PHY suspend. Places the ISP1507x1 ...
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Table 28. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface protect disable: Controls circuitry built into the ISP1507x1 to protect ...
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Table 29. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 6 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 0 Access R/W/S/C R/W/S/C Table 30. ...
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Table 31. USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation Bit 7 6 Symbol reserved Reset 0 0 Access R/W/S/C R/W/S/C Table 32. ...
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USB_INTR_STAT register This register (see Table 35. USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation Bit 7 6 Symbol reserved Reset X X Access R R Table 36. USB_INTR_STAT - USB Interrupt Status register (address ...
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Table 38. USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description Bit Symbol Description 2 SESS_VALID_L Session valid latch: Automatically set when an unmasked event occurs on SESS_VLD. Cleared when this register is read. 1 VBUS_VALID_L V ...
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PWR_CTRL register This register controls various aspects of the ISP1507x1. See Table 42. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation Bit 7 6 Symbol ...
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ElectroStatic Discharge (ESD) 12.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum of ±4 kV ESD protection. Capacitors 0.1 μF and 1 μF must be connected in parallel from V Remark: ...
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Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current ...
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Static characteristics Table 46. Static characteristics: supply pins CC(I/ Typical values are CC(I/O) Symbol Parameter V ...
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Table 47. Static characteristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, and CHIP_SELECT_N; unless otherwise specified CC(I/O) Typical values are at ...
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Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Output ...
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Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Termination ...
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Dynamic characteristics Table 55. Dynamic characteristics: reset and clock CC(I/ Typical values are CC(I/O) Symbol Parameter ...
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Table 56. Dynamic characteristics: digital I/O pins − ° 3 3 +85 CC amb Symbol Parameter 1.95 V CC(I/O) t DATA set-up time with respect ...
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Table 57. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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HSR 90% 90% 10 Fig 23. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL differential V ...
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Application information Table 58. Recommended list of materials [1] Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG R recommended; for ...
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V IN FAULT R pullup V BUS SWITCH ON OUT C bypass V BUS 1 D− USB MICRO-AB GND RECEPTACLE 5 SHIELD 6 SHIELD 7 8 ...
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V IN FAULT R pullup V BUS SWITCH OUT ON V BUS 1 D− USB 3 STANDARD-A RECEPTACLE GND 4 C VBUS SHIELD 5 SHIELD 6 f i(XTAL1) (1) ...
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C bypass R VBUS V 1 BUS D− USB STANDARD-B GND RECEPTACLE 4 SHIELD 5 SHIELD 6 C VBUS C bypass (1) Frequency is version dependent: ISP1507A1: 19.2 MHz; ...
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Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS ...
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Abbreviations Table 59. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS NRZI OTG PCB PHY PID PLD PLL POR RXCMD SE0 SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ [1] Physical ...
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References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN32 . ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Vendor ID and product ID registers . . . . . . . . 49 11.1.1.1 VENDOR_ID_LOW register . . . . . . . . . . . . . . 49 11.1.1.2 VENDOR_ID_HIGH register ...
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... Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 03 — 26 July 2010 ULPI HS USB OTG transceiver © ST-ERICSSON 2010. All rights reserved. ...