ISP1507ABS STEricsson, ISP1507ABS Datasheet
ISP1507ABS
Specifications of ISP1507ABS
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ISP1507ABS Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1507A; ISP1507B ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 19 May 2008 1. General description The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 ...
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... N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1507ABS) and 26 MHz (ISP1507BBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I ...
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... I Video camera 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1507ABS 507A 19.2 MHz [1] ISP1507BBS 507B 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1507A_ISP1507B_1 Product data sheet Package ...
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NXP Semiconductors 5. Block diagram 27 CLOCK 26, 8 28, 31, 32 DATA [7:0] ULPI INTERFACE 19 DIR 20 STP 21 NXT 29 CHIP_SELECT_N 17 RESET_N GLOBAL CLOCKS 15 XTAL1 16 XTAL2 2, 22, 30 interface voltage ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2] [3] Symbol Pin Type DATA0 1 I CC(I/O) RREF AI/O FAULT 6 I ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] [3] Symbol Pin Type V 13 AI/O BUS REG3V3 14 P XTAL1 15 AI XTAL2 16 AO RESET_N 17 I REG1V8 18 P DIR 19 O STP 20 I NXT 21 O ...
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NXP Semiconductors 7. Functional description 7.1 ULPI interface controller The ISP1507 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI interface ...
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NXP Semiconductors • Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode ...
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NXP Semiconductors • Resistors to temporarily charge and discharge V • Charge pump to provide 5 V power on V power from the ISP1507 V 7.6.1 ID detector The ID detector detects which end of the micro-USB cable is plugged ...
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NXP Semiconductors 7.6.4 Charge pump The ISP1507 uses a built-in charge pump to supply current The charge pump works as a capacitive DC-DC converter. An external holding capacitor, C which also shows a typical OTG ...
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NXP Semiconductors 7.9.2 V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CHIP_SELECT_N • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.9.3 RREF Resistor reference analog I/O ...
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NXP Semiconductors 7.9.8 C_A and C_B The C_A and C_B pins are to connect the flying capacitor of the charge pump. The output current capability of the charge pump depends on the value of the capacitor used, as shown in ...
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NXP Semiconductors The V BUS To prevent electrical overstress strongly recommended that you attach a series resistor on the V internal charge pump. For details, see 7.9.12 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to ...
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NXP Semiconductors 7.9.16 STP ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP to abort the ...
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NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1507 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one ...
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NXP Semiconductors Table 4. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1507 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that ...
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NXP Semiconductors Table 5. Signal mapping during low-power mode Signal Maps to Reserved DATA2 INT DATA3 Reserved DATA[7:4] 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed ...
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NXP Semiconductors Table 7. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than ...
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NXP Semiconductors Table 8. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Host low-speed 10b suspend Host low-speed 10b resume Host Test J or Test K 00b Peripheral settings Peripheral chirp 00b Peripheral 00b ...
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NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1507. 9.1 ULPI references The ISP1507 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin ...
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NXP Semiconductors If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 6. ...
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NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1507. The ISP1507 regulator starts to turn on. CC ...
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NXP Semiconductors The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1507 will ...
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NXP Semiconductors entering 3-state mode CLOCK CHIP_ SELECT_N DATA[7:0] DIR NXT STP Fig 8. Entering and exiting 3-state in normal mode CLOCK CHIP_ SELECT_N DATA[7:0] TXCMD DIR NXT STP SUSPENDM Remark: Clock timing is not to scale. Fig 9. Entering ...
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NXP Semiconductors 9.4 V power and fault detection BUS 9.4.1 Driving The ISP1507 provides a built-in charge pump. To enable the charge pump, the link must set the DRV_VBUS bit in the OTG_CTRL register (see The ...
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NXP Semiconductors Table 10. TXCMD byte format Command Command code type name DATA[7:6] Idle 00b Packet 01b transmit Register 10b write Register read 11b 9.5.2 RXCMD The ISP1507 communicates status information to the link by asserting DIR and sending an ...
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NXP Semiconductors CLOCK turnaround DATA [ 7:0 ] DIR STP NXT Fig 10. Single and back-to-back RXCMDs from the ISP1507 to the link 9.5.2.1 Linestate encoding LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1507 detects a ...
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NXP Semiconductors Table 13. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates ...
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NXP Semiconductors USE_EXT_VBUS_IND, IND_PASSTHRU Fig 11. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers. ...
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NXP Semiconductors OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 overcurrent ...
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NXP Semiconductors 9.6 Register read and write operations Figure 12 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly asserts DIR during the operation. When ...
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NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 ...
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NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR ...
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NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK DATA[7:0] TXCMD DIR STP NXT ...
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NXP Semiconductors Table 18. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK D ...
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NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 16. High-speed receive-to-transmit packet timing 9.9 ...
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NXP Semiconductors CLOCK DATA[7: Fig 17. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed or low-speed host-initiated suspend and resume Figure 18 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note ...
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NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 18. Full-speed suspend and ...
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NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1507 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN ...
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NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM ...
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NXP Semiconductors 9.10.3 Remote wake-up The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of ...
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NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 20. Remote ...
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NXP Semiconductors PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the ...
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NXP Semiconductors 9.12.1 OTG charge pump A description of the charge pump is given in configured as an A-device, it can provide the V Control of the charge pump is described in 9.12.2 OTG comparators The ISP1507 provides comparators that ...
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NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 22. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 ...
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NXP Semiconductors 9.14 Aborting transfers The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 . 9.15 Avoiding contention on the ULPI data bus Because the ULPI ...
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NXP Semiconductors 10. Register map Table 19. Immediate register set overview Field name Size (bit) VENDOR_ID_LOW 8 VENDOR_ID_HIGH 8 PRODUCT_ID_LOW 8 PRODUCT_ID_HIGH 8 FUNC_CTRL 8 INTF_CTRL 8 OTG_CTRL 8 USB_INTR_EN_R_E 8 USB_INTR_EN_F_E 8 USB_INTR_STAT 8 USB_INTR_L 8 DEBUG 8 SCRATCH ...
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NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 VENDOR_ID_LOW register Table 21 Table 21. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Bit Symbol Access VENDOR_ID_ R ...
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NXP Semiconductors Table 26. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. ...
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NXP Semiconductors Table 27. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit allocation Bit 7 Symbol INTF_ IND_PASS PROT_DIS THRU Reset 0 Access R/W/S/C R/W/S/C Table 28. ...
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NXP Semiconductors 10.1.4 OTG_CTRL register This register controls various OTG functions of the ISP1507. The bit allocation of the OTG_CTRL register is given in Table 29. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah, ...
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NXP Semiconductors Table 30. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description …continued Bit Symbol Description 2 DM_PULLDOWN DM Pull Down: Enables the 15 k pull-down ...
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NXP Semiconductors Table 33. USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit allocation Bit 7 Symbol reserved Reset 0 Access R/W/S/C R/W/S/C Table 34. ...
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NXP Semiconductors Remark optional for the link to read this register when the clock is running because all signal information will automatically be sent to the link through the RXCMD byte. The bit allocation of this register is ...
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NXP Semiconductors Table 41. SCRATCH - Scratch register (address R = 16h to 18h 16h 17h 18h) bit description Bit Symbol Access Value Description SCRATCH R/W/S/C 00h [7:0] 10.1.11 Reserved Registers ...
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NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from ...
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NXP Semiconductors 12. Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I ...
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NXP Semiconductors 14. Static characteristics Table 46. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 47. Static characteristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N and CHIP_SELECT_N; unless otherwise specifi CC(I/O) Typical values ...
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NXP Semiconductors Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 53. Static characteristics CC(I/O) Typical values are 3 Symbol Parameter R pull-up resistance on ...
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NXP Semiconductors 120 I CC(cp) (mA) 100 = denotes charge pump supply current. CC(cp) Fig 25. Charge pump supply current as a function ...
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... CC(I/O) amb Conditions 4 capacitor each on pins REG1V8 and REG3V3 ISP1507ABS ISP1507BBS ISP1507ABS ISP1507BBS applicable only when clock is applied on pin XTAL1 only for square wave input only for square wave input only for square wave input measured from power good or assertion of pin STP Rev. 01 — ...
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NXP Semiconductors Table 57. Dynamic characteristics: digital I/O pins +85 C; unless otherwise specified. CC amb Symbol Parameter 1.95 V CC(I/O) t DATA ...
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NXP Semiconductors Table 58. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Typical values are 3 Symbol ...
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NXP Semiconductors HSR Fig 29. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential ...
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NXP Semiconductors 16. Application information Table 59. Recommended bill of materials [1] Designator Application C highly recommended for all bypass applications C charge pump is used cp(C_A)-(C_B) C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory ...
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... MICRO- RECEPTACLE IP4359CX4/LF SHIELD ESD SHIELD 7 8 SHIELD 9 SHIELD C VBUS C bypass (1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz. Fig 34. Using the ISP1507 with an OTG controller; internal charge pump is utilized and crystal is attached V CC(I/O) DATA1 DATA0 DATA2 V CC(I/ RREF V RREF CC(I/O) ...
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... C VBUS SHIELD 5 SHIELD IP4359CX4/ i(XTAL1) (1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz. Fig 35. Using the ISP1507 with a standard USB host controller; external 5 V source with built-in FAULT and external square wave input on XTAL1 V V CC(I/ bypass DATA1 DATA0 DATA2 ...
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... BUS USB STANDARD-B GND RECEPTACLE SHIELD IP4359CX4/ SHIELD 6 D ESD C bypass (1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz. Fig 36. Using the ISP1507 with a standard USB peripheral controller; external crystal V V CC(I/O) CC DATA1 DATA0 1 32 DATA2 V CC(I/ RREF RREF 3 30 CHIP_SELECT_N ...
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NXP Semiconductors 17. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area ...
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NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction ...
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NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 38. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 62. Acronym ASIC ATX CD-RW EOP ESD ESR FS ...
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NXP Semiconductors Table 62. Acronym PLL POR RXCMD SE0 SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ [1] Physical layer containing the USB transceiver. The ISP1507 is a PHY. 20. References [1] Universal Serial Bus Specification Rev. 2.0 ...
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NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
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NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 Immediate register set . . . . ...