ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 11

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
8.4 Voltage regulator
8.5 Crystal oscillator and PLL
8.6 UART buffer
For details on controlling resistor settings, see
The ISP1705 contains a built-in voltage regulator that conditions the V
inside the ISP1705. The voltage regulator:
The ISP1705 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation. When a crystal is in use, the built-in crystal oscillator generates a square wave
clock for internal use. A square wave clock of the same frequency can also be driven
directly into the XTAL1 pin. Using an existing square wave clock can save the cost of a
crystal and also reduce the board space. The crystal or clock frequencies supported are
13 MHz, 19.2 MHz, 24 MHz and 26 MHz.
The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it
into various frequencies for internal use.
The PLL produces the following frequencies, irrespective of the clock source:
The UART buffer includes circuits to support the transparent UART signaling between the
DATA0 or DATA1 pin and the DM or DP pin.
When the ISP1705 is put into UART mode, it acts as a voltage level shifter between the
following pins:
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High-speed disconnect detector
45
1.5 k
15 k bus terminations on pins DP and DM
Supports input supply range 3.0 V < V
Can be supplied from a battery with the voltage range mentioned above.
Supplies internal digital circuitry with 1.8 V and analog circuitry with 3.3 V or 2.7 V.
In USB mode, automatically bypasses the internal 3.3 V regulator when V
the internal analog circuitry directly draws power from the V
bypass switch will be disabled.
Will be shut down when V
1.5 MHz for low-speed USB data
12 MHz for full-speed USB data
60 MHz clock for the ULPI interface controller
480 MHz for high-speed USB data
Other internal frequencies for data conversion and data recovery
From DATA0 (V
From DP (2.7 V level) to DATA1 (V
high-speed bus terminations on pins DP and DM
pull-up resistor on pin DP
CC(I/O)
Rev. 02 — 21 January 2009
level) to DM (2.7 V level) for the UART TXD signaling path.
CC(I/O)
is not present or when chip select is deasserted.
CC(I/O)
CC
< 4.5 V.
level) for the UART RXD signaling path.
Table
15.
ULPI Hi-Speed USB transceiver
CC
pin. In UART mode, the
© ST-NXP Wireless 2009. All rights reserved.
CC
ISP1705
supply for use
CC
< 3.5 V:
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