ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 20

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
8.12.12 XTAL1 and XTAL2
8.12.11 PSW_N
The PSW_N pin is an active-LOW open-drain output pin. It is used to control external
charge pumps or V
resistor is required. This allows for per-port or ganged power control.
To enable the external power source by driving PSW_N to LOW, the link must set the
DRV_VBUS_EXT bit in the OTG_CTRL register (see
Table 5
Table 5.
XTAL1 is the crystal oscillator input, and XTAL2 is the crystal oscillator output. The
allowed crystal or clock frequency on the XTAL1 pin is selectable by the CFG1 and CFG2
pins, as shown in
Table 6.
When a clock is driven into XTAL1, XTAL2 must be left open.
DRV_VBUS_EXT
0
1
Pin CFG1
LOW
LOW
HIGH
HIGH
Fig 9.
summarizes settings to drive 5 V on V
V
BUS
OTG_CTRL register power control bits
Allowed crystal or clock frequency on the XTAL1 pin
pin internal pull-up and pull-down scheme
Pin CFG2
LOW
HIGH
LOW
HIGH
Table
BUS
Power source used
external 5 V V
external 5 V V
Rev. 02 — 21 January 2009
power switches to supply V
V
comparators
6.
BUS
BUS
BUS
Allowed crystal or clock frequency on the XTAL1 pin
19.2 MHz
26 MHz
24 MHz
13 MHz
R DN(VBUS)
CHRG_VBUS
R UP(VBUS)
DISCHRG_
VBUS
power source disabled (PSW_N = HIGH)
power source enabled (PSW_N = LOW)
ISP1705
BUS
R I(idle)(VBUS)
.
BUS
004aab045
Section
. When in use, an external pull-up
ULPI Hi-Speed USB transceiver
11.7) to logic 1.
REG3V3
V
BUS
© ST-NXP Wireless 2009. All rights reserved.
ISP1705
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