ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 21

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
8.12.13 DIR
8.12.14 RESET_N
8.12.15 STP
8.12.16 NXT
If a crystal is attached, it requires a capacitor on each terminal of the crystal to GND. The
recommended crystal specification and required external capacitors are given in
and
Table 7.
[1]
Table 8.
[1]
ULPI direction output pin. Synchronous to the rising edge of CLOCK. Controls the
direction of the data bus. By default, the ISP1705 holds DIR at LOW, causing the data bus
to be an input. When DIR is LOW, the ISP1705 listens for data from the link. The ISP1705
pulls DIR to HIGH only when it has data to send to the link, which is for one of two
reasons:
This pin can be 3-stated when chip select is deasserted.
An active-LOW asynchronous reset pin that resets all circuits in the ISP1705. The
ISP1705 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP
to signal the end of a USB transmit packet or a register write operation. When DIR is
asserted, the link can optionally assert STP for one clock cycle to abort the ISP1705,
causing it to deassert DIR in the next clock cycle.
ULPI next data output pin. Synchronous to the rising edge of CLOCK. The ISP1705 holds
NXT at LOW, by default. When DIR is LOW and the link is sending data to the ISP1705,
NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH
Load capacitance C
crystal
10 pF
20 pF
Load capacitance C
crystal
10 pF
20 pF
•
•
Specified by the crystal manufacturer.
Specified by the crystal manufacturer.
To send data (USB receive or register reads) and RXCMD status updates to the link.
To block the link from driving the data bus during power-up, reset and low power
(suspend) mode.
Table
[1]
[1]
8.
External capacitor values for 13 MHz or 19.2 MHz clock frequency
External capacitor values for 24 MHz or 26 MHz clock frequency
L
L
of the
of the
Rev. 02 — 21 January 2009
Maximum series resistance R
the crystal
< 180
< 100
Maximum series resistance R
the crystal
< 140
< 60
Section
[1]
[1]
8.11.2.
ULPI Hi-Speed USB transceiver
S
S
of
of
CC(I/O)
External capacitor
C
18 pF
39 pF
External capacitor
C
18 pF
39 pF
© ST-NXP Wireless 2009. All rights reserved.
XTAL
XTAL
.
ISP1705
value
value
Table 7
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