ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 22

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
8.12.17 CLOCK
8.12.18 CFG1, CFG2
8.12.19 CHIP_SEL, CHIP_SEL_N
8.12.20 GND
and the ISP1705 is sending data to the link, NXT will be asserted to notify the link that
another valid byte is on the bus. NXT is not used for register read data or the RXCMD
status update.
This pin can be 3-stated when chip select is deasserted.
A 60 MHz interface clock to synchronize the ULPI bus. All ULPI pins are synchronous to
the rising edge of CLOCK.
The ISP1705 provides two clocking options:
These input pins are used to select the crystal or clock frequency. For details, see
When chip select is deasserted, ULPI pins DATA[7:0], CLOCK, DIR and NXT are 3-stated
and the STP input is ignored; internal circuits are powered-down as well.
When chip select is asserted, the ISP1705 will operate normally.
Both the CHIP_SEL and CHIP_SEL_N pins must be asserted for the chip select to
function. If any of the two is deasserted, the chip will enter Power-down mode.
Global ground signal. To ensure the correct operation of the ISP1705, GND must be
soldered to the cleanest available ground.
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A crystal is attached between the XTAL1 and XTAL2 pins.
A clock is driven into the XTAL1 pin, with the XTAL2 pin left unconnected.
Rev. 02 — 21 January 2009
ULPI Hi-Speed USB transceiver
© ST-NXP Wireless 2009. All rights reserved.
ISP1705
Table
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6.