ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 24

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

Table 10.
ISP1705_2
Product data sheet
Signal name
CLOCK
DATA[7:0]
ULPI signal description
9.2.1 Synchronous mode
Direction on
the ISP1705
O
I/O
9.2 ULPI modes
When the ISP1705 is put into Power-down mode by disabling chip select, all the digital
pins (see
inputs. These pins must be driven to defined states or terminated by using pull-up or
pull-down resistors to avoid a floating input condition. Other pins (see
not powered. In this mode, minimum current will be drawn by V
select status.
The ISP1705 ULPI interface can be programmed to operate in five modes. In each mode,
the signals on the data bus are reconfigured as described in the following subsections.
Setting more than one mode will lead to undefined behavior.
This is default mode. On power-up, and when CLOCK is stable, the ISP1705 will enter
synchronous mode.
In synchronous mode, the link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
•
•
•
•
[1]
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read from and write to registers
Receive USB status updates (RXCMDs) from the ISP1705
Signal description
60 MHz interface clock: When a crystal is attached or a clock is driven into the XTAL1
pin, the ISP1705 will drive a 60 MHz output clock.
During low-power, serial and UART modes, the clock can be turned off to save power.
8-bit data bus: In synchronous mode, the link drives DATA[7:0] to LOW by default. The
link initiates transfers by sending a nonzero data pattern called a TXCMD (transmit
command). In synchronous mode, the direction of DATA[7:0] is controlled by DIR.
Contents of DATA[7:0] lines must be ignored for exactly one clock cycle whenever DIR
changes state. This is called a turnaround cycle.
Data lines have fixed directions and different meanings in low-power, 3-pin serial and
UART modes.
Section
8.12.2) that are powered by V
Rev. 02 — 21 January 2009
Section
15.
CC(I/O)
are configured as high-impedance
ULPI Hi-Speed USB transceiver
CC(I/O)
© ST-NXP Wireless 2009. All rights reserved.
Section
to detect the chip
Section
ISP1705
10.
8.12.9) are
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