ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 38

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the FUNC_CTRL register (see
XCVRSELECT[1:0] = 00b (high speed) and TERMSELECT = 0b that drives SE0 on
the bus (DP and DM connected to ground through 45 ). The host also sets
OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled
t0.
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE as shown in
Table
a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is
b. Host chirp: If the host does not detect the peripheral chirp, it must continue
c. High speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each
capable of high speed, it sets XCVRSELECT[1:0] to 00b (high speed) and
OPMODE[1:0] to 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
than 7 ms after reset time t0. If the peripheral is in low-power mode, it must wake
up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for
no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K
state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks
and Js. Each Chirp K or Chirp J must last no less than 40 s and no longer than
60 s.
Chirp K and Chirp J must be detected for at least 2.5 s. The peripheral sets
TERMSELECT = 0b and OPMODE[1:0] = 00b after seeing the minimum chirp
sequence. The peripheral is now in high-speed mode and sees !squelch (01b on
LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows
that the host has completed chirp and waits for Hi-Speed USB traffic to begin. After
transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and
begins sending USB packets.
19.
Rev. 02 — 21 January 2009
ULPI Hi-Speed USB transceiver
Section
11.5) and setting
© ST-NXP Wireless 2009. All rights reserved.
ISP1705
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