ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 56

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

Table 32.
ISP1705_2
Product data sheet
Bit
Symbol
Reset
Access
INTF_CTRL - Interface control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
PROT_DIS
R/W/S/C
INTF_
11.6 INTF_CTRL register
7
0
The INTF_CTRL register enables alternative interfaces. All of these modes are optional
features provided for legacy link cores. Setting more than one of these fields results in
undefined behavior.
Table 33.
Bit
7
6
5
4
3
IND_PASS
R/W/S/C
THRU
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_SUSPENDM
6
0
INTF_CTRL - Interface control register (address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit description
R/W/S/C
COMPL
IND_
5
0
Table 32
Rev. 02 — 21 January 2009
Description
Interface protect disable: Controls circuitry built into the ISP1705
to protect the ULPI interface when the link 3-states STP and
DATA[7:0]. When this bit is enabled, the ISP1705 will automatically
detect when the link stops driving STP.
0b — Enables the interface protect circuit. The ISP1705 attaches
a weak pull-up resistor on STP. If STP is unexpectedly HIGH, the
ISP1705 attaches weak pull-down resistors on DATA[7:0],
protecting data inputs
1b — Disables the interface protect circuit, detaches weak
pull-down resistors on DATA[7:0], and a weak pull-up resistor on
STP
Indicator pass-through: Controls whether the complement output
is qualified with the internal A_VBUS_VLD comparator before
being used in the V
0b — The complement output signal is qualified with the internal
A_VBUS_VLD comparator
1b — The complement output signal is not qualified with the
internal A_VBUS_VLD comparator
Indicator complement: Informs the PHY to invert the FAULT input
signal, generating the complement output.
0b — The ISP1705 will not invert the FAULT signal
1b — The ISP1705 will invert the FAULT signal
reserved
Clock suspend: Active-LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock
will not be powered in 6-pin serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only
when SUSPENDM is set to logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode or
UART mode
1b — Clock will be powered in 3-pin and 6-pin serial mode or
UART mode
reserved
R/W/S/C
provides the bit allocation of the register.
4
0
SUSPENDM
CLOCK_
R/W/S/C
3
0
BUS
state in RXCMD.
CARKIT_
R/W/S/C
MODE
ULPI Hi-Speed USB transceiver
2
0
R/W/S/C
© ST-NXP Wireless 2009. All rights reserved.
SERIAL
FSLS_
3PIN_
1
0
ISP1705
R/W/S/C
SERIAL
FSLS_
6PIN_
0
0
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