ISP1507EBSUM STEricsson, ISP1507EBSUM Datasheet
ISP1507EBSUM
Specifications of ISP1507EBSUM
Related parts for ISP1507EBSUM
ISP1507EBSUM Summary of contents
Page 1
ISP1507E; ISP1507F ULPI Hi-Speed USB On-The-Go transceiver Rev. 04 — 20 May 2010 1. General description The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement ...
Page 2
Integrated 5 V charge pump; also supports external charge pump switch Complete control over bus resistors Data line and V Integrated V Integrated cable (ID) detector Highly optimized ULPI compliant 60 MHz, 8-bit interface between the ...
Page 3
... Ordering information Table 1. Ordering information Commercial Marking Crystal or product code clock frequency [1] ISP1507EBSUM 07E 19.2 MHz [1] ISP1507FBSUM 07F 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. CD00222691 Product data sheet ISP1507E; ISP1507F Package description Packing HVQFN24 ...
Page 4
Block diagram 19 CLOCK 17 STP 16 DIR ULPI INTERFACE 18 NXT 20, 22, 23 DATA[3:0] 14 RESET_N/ PSW_N global clocks 12 XTAL1 13 XTAL2 CC(I/O) 11 REG3V3 15 REG1V8 Fig ...
Page 5
Pinning information 6.1 Pinning Fig 2. Pin configuration HVQFN24; top view 6.2 Pin description Table 2. Pin description [1][2][3] [4] Symbol Pin Type Description I/O supply rail CC(I/O) RREF 2 AI/O resistor reference DM 3 AI/O ...
Page 6
Table 2. Pin description …continued [1][2][3] [4] Symbol Pin Type Description XTAL1 12 AI crystal oscillator or clock input XTAL2 13 AO crystal oscillator output RESET_N/ 14 I/O This pin has two possible functions: PSW_N RESET_N (input) — Active LOW ...
Page 7
Functional description 7.1 ULPI controller The ISP1507 provides an 8-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to the USB link. The ULPI controller provides the following functions: ...
Page 8
Squelch circuit to detect high-speed bus activity • High-speed disconnect detector 45 Ω high-speed bus terminations on DP and DM for peripheral and host modes • • 1.5 kΩ pull-up resistor on DP for full-speed peripheral mode • 15 ...
Page 9
Charge pump to provide 5 V power on V power from the ISP1507 V 7.6.1 ID detector The ID detector detects which end of the micro-USB cable is plugged in. The detector must first be enabled by setting the ...
Page 10
OTG V amount of current drive required. If the internal charge pump is not used, the C capacitor is not required. For details on the C_A and C_B pins, see Fig 3. External capacitors connection ...
Page 11
STP 7.9.3 RREF Resistor reference analog I/O pin. A resistor, R and GND, as shown in biases internal analog circuitry. Less accurate resistors cannot be used and will render the ISP1507 unusable. 7.9.4 DP and DM DP (data plus) ...
Page 12
Table 3. C cp(C_A)-(C_B 270 nF 7.9 the main input supply voltage for the ISP1507. Decoupling capacitors are CC recommended. For details, see 7.9.9 V /FAULT BUS This pin provides two options for V ...
Page 13
RESET_N/PSW_N This pin provides two optional functions. If neither function is used, this pin must be connected to V 7.9.12.1 RESET_N An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The ISP1507 contains an internal ...
Page 14
NXT ULPI next data output pin. The ISP1507 holds NXT at LOW by default. When DIR is LOW and the link is sending data to the ISP1507, NXT will be asserted to notify the link to provide the next ...
Page 15
Modes of operation 8.1 ULPI modes The ISP1507 ULPI bus can be programmed to operate in three modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will ...
Page 16
Table 4. ULPI signal description Signal name Direction on Signal description ISP1507 DIR O Direction: Controls the direction of data bus DATA[3:0]. In synchronous mode, the ISP1507 drives DIR to LOW by default, making the data bus an input so ...
Page 17
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1507 to 3-pin serial mode. In 3-pin serial mode, the data bus ...
Page 18
Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] General settings 3-state drivers XXb Xb Power-up or 01b 0b V < V BUS B_SESS_END Host settings Host chirp 00b 0b Host ...
Page 19
Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] OTG device 01b 1b peripheral high-speed and full-speed suspend OTG device 01b 1b peripheral high-speed and full-speed resume OTG device 00b 0b ...
Page 20
Protocol description The following subsections describe the protocol for using the ISP1507. Remark: In all figures, the ULPI data is shown in a generic form and not as nibbles on the rising and falling edges of the clock. 9.1 ...
Page 21
After every reset, an RXCMD is sent to the link to update USB status information. After this sequence, the ULPI bus is ready for use and the link can start USB operations. When the internal PLL is ...
Page 22
CC(I/O) REG1V8 t REGUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[3:0] DIR STP NXT and V are applied to the ISP1507. The ISP1507 regulator starts to turn on. CC CC(I/O) t2 ...
Page 23
The interface protect feature prevents unwanted activity of the ISP1507 whenever the ULPI is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1507. The interface protect feature can be disabled by ...
Page 24
Table 8. DRV_VBUS 9.4.2 Fault detection The ISP1507 supports external V indicator signal. The indicator signal must be connected to the FAULT pin. To enable the ISP1507 to monitor the digital fault input, the link must set ...
Page 25
RXCMD The ISP1507 communicates status information to the link by asserting DIR and sending an RXCMD byte on the data bus. The RXCMD data byte format is given in The ISP1507 will automatically send an RXCMD whenever there is ...
Page 26
Table 11. LINESTATE[1:0] encoding for upstream facing ports: peripheral [1] DP_PULLDOWN = 0. Mode Full-speed XCVRSELECT[1:0] 01, 11 TERMSELECT 1 LINESTATE[1:0] 00 SE0 01 FS-J 10 FS-K 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. Table 12. ...
Page 27
V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 9. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB_INTR_EN_R_E and ...
Page 28
OTG devices: provide a minimum then there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 ...
Page 29
Register read and write operations Figure 10 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly asserts DIR during the operation. When a register ...
Page 30
High-speed detection handshake (chirp) a. Peripheral chirp: After detecting SE0 for no less than 2.5 μs, if the peripheral is capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this ...
Page 31
USB reset T 0 TXCMD (REGW) SE0 DATA [ 3:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD (REGW) SE0 DATA [ 3:0 ] DIR STP NXT ...
Page 32
USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD CLOCK DATA [ 3:0 ] TXCMD DIR STP NXT ...
Page 33
Allowed link decision time The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in values given in packet sequences and timing are shown in UTMI+ Low ...
Page 34
DP or DATA DM CLOCK D D N−1 N DATA [3:0] DIR STP NXT TX end delay (two to five clocks) Fig 13. High-speed transmit-to-transmit packet timing DP or DATA EOP DM CLOCK N−4 N−2 N DATA ...
Page 35
Preamble Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see preamble mode, the ...
Page 36
Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state. The peripheral link places the PHY into low-power mode by clearing the SUSPENDM bit in the FUNC_CTRL register (see draw only suspend current. ...
Page 37
DATA [ 3:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT OPMODE SUSPENDM LINE J STATE DP DM Timing is not to scale. Fig 16. Full-speed suspend and ...
Page 38
The sequence of events related to a host and a peripheral, both with ISP1507 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN ...
Page 39
HS idle TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP 00b MODE !squelch squelch (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT ...
Page 40
Remote wake-up The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols ...
Page 41
LINESTATE DATA [ 3:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 3:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 18. Remote wake-up from ...
Page 42
PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must ...
Page 43
OTG charge pump A description of the charge pump is given in configured as an A-device, it can provide the V Control of the charge pump is described in 9.12.2 OTG comparators The ISP1507 provides comparators that conform to ...
Page 44
SYNC DATA0 (TX_ENABLE) DATA1 (DAT) DATA2 (SE0 Fig 20. Example of transmit followed by receive in 3-pin serial mode 9.14 Aborting transfers The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin ...
Page 45
Register map Table 18. Immediate register set overview Field name VENDOR_ID_LOW VENDOR_ID_HIGH PRODUCT_ID_LOW PRODUCT_ID_HIGH FUNC_CTRL INTF_CTRL OTG_CTRL USB_INTR_EN_R_E USB_INTR_EN_F_E USB_INTR_STAT USB_INTR_L DEBUG SCRATCH Reserved (do not use) Access extended register set Vendor-specific register PWR_CTRL [1] Read (R): A register ...
Page 46
Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 VENDOR_ID_LOW register Table 20 shows the bit description of the register. Table 20. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Legend: * reset ...
Page 47
Table 25. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the ...
Page 48
Table 27. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1507 to protect ...
Page 49
Table 29. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_ Use External V VBUS_IND 0b — Use the internal OTG comparator ...
Page 50
Table 31. USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved 4 ID_GND_R ID Ground Rise: ...
Page 51
Table 34. USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation Bit 7 6 Symbol reserved Reset X X Access R R Table 35. USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description Bit ...
Page 52
DEBUG register The bit allocation of the DEBUG register is given in current value of signals useful for debugging. Table 38. DEBUG - Debug register (address R = 15h) bit allocation Bit 7 6 Symbol Reset 0 0 Access ...
Page 53
Table 41. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation Bit 7 6 Symbol Reset 0 0 Access R/W/S/C R/W/S/C Table 42. PWR_CTRL - Power Control ...
Page 54
ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum of ±4 kV ESD protection. Capacitors 0.1 μF and 1 μF must be connected in parallel from V Remark: ...
Page 55
Limiting values Table 43. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current ...
Page 56
Static characteristics Table 45. Static characteristics: supply pins CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V ...
Page 57
Table 46. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[3:0], RESET_N/PSW_N CC(I/O) Typical values are 3 CC(I/O) ...
Page 58
Table 48. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Termination ...
Page 59
Table 49. Static characteristics: charge pump CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Voltage V output voltage ...
Page 60
Table 53. Static characteristics: resistor reference CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V output voltage on ...
Page 61
Dynamic characteristics Table 54. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
Page 62
Table 55. Dynamic characteristics: digital I/O pins CC(I/O) Symbol Parameter t DATA set-up time with respect to su(DATA) the rising edge of pin CLOCK ...
Page 63
Table 56. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Symbol Parameter t driver disable delay from PHZ HIGH level t driver disable ...
Page 64
CLOCK CONTROL IN DATA IN (4-BIT) CONTROL OUT (DIR, NXT) DATA OUT (4-BIT) Fig 30. ULPI timing CD00222691 Product data sheet t t su(STP) h(STP) (STP su(DATA) h(DATA su(DATA) h(DATA) Rev. 04 — 20 May 2010 ...
Page 65
Application information Table 57. Recommended list of materials [1] Designator Application C highly recommended for bypass all applications C charge pump is used cp(C_A)-(C_B) C highly recommended for filter all applications C mandatory for peripherals VBUS mandatory for host ...
Page 66
V BUS 1 D− USB MINI-AB GND RECEPTACLE 5 SHIELD 6 SHIELD 7 SHIELD 8 SHIELD 9 C VBUS (1) Frequency is version dependent: ISP1507E: 19.2 MHz; ...
Page 67
IN +3 pullup CHARGE PUMP ON V BUS 1 D− USB MINI-AB RECEPTACLE GND 5 SHIELD 6 SHIELD 7 SHIELD 8 SHIELD 9 (1) Frequency ...
Page 68
pullup FAULT V BUS SWITCH OUT ON V BUS 1 D− USB 3 STANDARD-A RECEPTACLE GND 4 SHIELD 5 SHIELD 6 C VBUS C bypass (1) ...
Page 69
V BUS 1 D− USB STANDARD-B RECEPTACLE GND 4 SHIELD 5 SHIELD 6 C bypass (1) Frequency is version dependent: ISP1507E: 19.2 MHz; ISP1507F: 26 MHz. Fig 34. Using ...
Page 70
Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS ...
Page 71
Abbreviations Table 58. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS NRZI OTG PCB PHY PID PLD PLL POR RXCMD SE0 SOF SRP SYNC TTL TXCMD ULPI USB USB-IF UTMI UTMI+ 19. References ...
Page 72
UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05 [6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) [7] Interfacing to the ISP1507 (AN10080) 20. Revision history Table 59. Revision history Revision ...
Page 73
Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . ...
Page 74
Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN24; top ...
Page 75
Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
Page 76
Vendor ID and Product ID registers . . . . . . . . 46 10.1.1.1 VENDOR_ID_LOW register . . . . . . . . . . . . . . 46 10.1.1.2 VENDOR_ID_HIGH register ...
Page 77
... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 04 — 20 May 2010 ISP1507E; ISP1507F ULPI HS USB OTG transceiver © ...