ISP1507FBS,518 NXP Semiconductors, ISP1507FBS,518 Datasheet
ISP1507FBS,518
Specifications of ISP1507FBS,518
Related parts for ISP1507FBS,518
ISP1507FBS,518 Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1507E; ISP1507F ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 28 May 2008 1. General description The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 ...
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... NXP Semiconductors N Integrated 5 V charge pump; also supports external charge pump switch N Complete control over bus resistors N Data line and V N Integrated V N Integrated cable (ID) detector I Highly optimized ULPI compliant N 60 MHz, 8-bit interface between the core and the transceiver N Supports 4-bit dual-edge data bus N Supports 60 MHz output clock confi ...
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... NXP Semiconductors I Set-Top Box (STB) I Video camera 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1507EBS 07E 19.2 MHz [1] ISP1507FBS 07F 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ...
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... NXP Semiconductors 5. Block diagram 19 CLOCK 17 STP 16 DIR ULPI INTERFACE 18 NXT 20, 22, 23 DATA[3:0] 14 RESET_N/ PSW_N global clocks 12 XTAL1 13 XTAL2 CC(I/O) 11 REG3V3 15 REG1V8 Fig 1. Block diagram ISP1507E_ISP1507F_1 Product data sheet USB DATA SERIALIZER ULPI INTERFACE CONTROLLER USB DATA DESERIALIZER V valid external BUS REGISTER ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2][3] [4] Symbol Pin Type CC(I/O) RREF CPGND 6 P C_B 7 AI/O C_A 8 AI /FAULT 10 AI/O BUS REG3V3 11 P XTAL1 12 AI XTAL2 13 AO ISP1507E_ISP1507F_1 Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2][3] [4] Symbol Pin Type RESET_N/ 14 I/O PSW_N REG1V8 15 P DIR 16 O STP 17 I NXT 18 O CLOCK 19 O DATA3 20 I CC(I/O) DATA2 22 I/O DATA1 23 I/O DATA0 24 I/O GND die P pad [1] A detailed description of these pins can be found in [2] Symbol names ending with an underscore N (for example, NAME_N) indicate active LOW signals ...
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... NXP Semiconductors 7. Functional description 7.1 ULPI controller The ISP1507 provides an 8-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI controller provides the following functions: • ULPI-compliant interface and register set • ...
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... NXP Semiconductors • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode • bus terminations on DP and DM for host and OTG modes For details on controlling resistor settings, see 7.4 Voltage regulator The ISP1507 contains a built-in voltage regulator that conditions the V inside the ISP1507 ...
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... NXP Semiconductors • Charge pump to provide 5 V power on V power from the ISP1507 V 7.6.1 ID detector The ID detector detects which end of the micro-USB cable is plugged in. The detector must first be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1507 senses a value on ID that is different from the previously reported value, an RXCMD status update will be sent to the USB link interrupt will be asserted. • ...
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... NXP Semiconductors which also shows a typical OTG V amount of current drive required. If the internal charge pump is not used, the C capacitor is not required. For details on the C_A and C_B pins, see Fig 3. 7.7 Band gap reference voltage The band gap circuit provides a stable internal voltage reference to bias the analog circuitry ...
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... NXP Semiconductors • STP 7.9.3 RREF Resistor reference analog I/O pin. A resistor, R and GND, as shown in biases internal analog circuitry. Less accurate resistors cannot be used and will render the ISP1507 unusable. 7.9.4 DP and DM DP (data plus) and DM (data minus) are USB differential data pins. These must be connected to the D+ and D pins of the USB receptacle ...
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... NXP Semiconductors Table 3. C cp(C_A)-(C_B 270 nF 7.9 the main input supply voltage for the ISP1507. Decoupling capacitors are CC recommended. For details, see 7.9.9 V /FAULT BUS This pin provides two options for V this pin must be connected to ground. 7.9.9.1 V BUS This pin acts as an input to V pump, and SRP charge and discharge resistors ...
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... NXP Semiconductors 7.9.12 RESET_N/PSW_N This pin provides two optional functions. If neither function is used, this pin must be connected to V 7.9.12.1 RESET_N An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N pin is optional ...
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... NXP Semiconductors 7.9.15 NXT ULPI next data output pin. The ISP1507 holds NXT at LOW by default. When DIR is LOW and the link is sending data to the ISP1507, NXT will be asserted to notify the link to provide the next data byte. When DIR is at HIGH and the ISP1507 is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus ...
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... NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1507 ULPI bus can be programmed to operate in three modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will lead to undefined behavior. 8.1.1 Synchronous mode This is default mode ...
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... NXP Semiconductors Table 4. ULPI signal description Signal name Direction on Signal description ISP1507 DIR O Direction: Controls the direction of data bus DATA[3:0]. In synchronous mode, the ISP1507 drives DIR to LOW by default, making the data bus an input so that the ISP1507 can listen for TXCMDs from the link. The ISP1507 drives DIR to HIGH only when it has data for the link ...
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... NXP Semiconductors 8.1.3 3-pin full-speed or low-speed serial mode If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1507 to 3-pin serial mode. In 3-pin serial mode, the data bus definition changes to that shown in 3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see 3-pin serial mode, the link asserts STP ...
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... NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] General settings 3-state drivers XXb Power-up or 01b V < V BUS B_SESS_END Host settings Host chirp 00b Host high-speed 00b Host full-speed X1b Host high-speed or 01b ...
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... NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] OTG device 01b peripheral high-speed and full-speed suspend OTG device 01b peripheral high-speed and full-speed resume OTG device 00b peripheral Test J or Test K ISP1507E_ISP1507F_1 ...
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... NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1507. Remark: In all figures, the ULPI data is shown in a generic form and not as nibbles on the rising and falling edges of the clock. 9.1 ULPI references The ISP1507 provides an 8-pin ULPI to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) Specifi ...
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... NXP Semiconductors reset has completed. After every reset, an RXCMD is sent to the link to update USB status information. After this sequence, the ULPI bus is ready for use and the link can start USB operations. When the internal PLL is stable, the ISP1507 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts ...
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... NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[3:0] DIR STP NXT and V are applied to the ISP1507. The ISP1507 regulator starts to turn on. CC CC(I/ ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive either LOW or HIGH recommended that the link ignores the ULPI pins status during The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defi ...
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... NXP Semiconductors The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1507 will assert DIR. All logic in the ISP1507 will be reset, including the analog circuitry and ULPI registers. During reset, the link must drive DATA[3:0] and STP to LOW ...
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... NXP Semiconductors 9.4.2 Fault detection The ISP1507 supports external V indicator signal. The indicator signal must be connected to the FAULT pin. To enable the ISP1507 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit in the OTG_CTRL register (see INTF_CTRL register (see The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD ...
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... NXP Semiconductors The ISP1507 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fields. The link must be able to accept an RXCMD at any time; including single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive packets when NXT is LOW. An example is shown in refer to UTMI+ Low Pin Interface (ULPI) Specifi ...
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... NXP Semiconductors Table 11. LINESTATE[1:0] encoding for upstream facing ports: peripheral [1] DP_PULLDOWN = 0. Mode Full-speed XCVRSELECT[1:0] 01, 11 TERMSELECT 1 LINESTATE[1:0] 00 SE0 01 FS-J 10 FS-K 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. Table 12. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode ...
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... NXP Semiconductors V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 9. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers. The link can use the V shows the recommended usage for typical applications ...
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... NXP Semiconductors Standard USB peripheral controllers: when V start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END thresholds is not needed for standard peripherals. OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 ...
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... NXP Semiconductors enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers, respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the link with the updated value. 9.6 Register read and write operations Figure 10 addressing and extended addressing register operations. Extended register addressing is optional for links ...
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... NXP Semiconductors 2. High-speed detection handshake (chirp) a. Peripheral chirp: After detecting SE0 for no less than 2 the peripheral is capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more than 7 ms after reset time T up its clock within 5 ...
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... NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 3:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE SE0 (00b) J (01b) LINE STATE TXCMD (REGW) SE0 DATA [ 3:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) ...
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... NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD DIR STP NXT Fig 12. Example of using the ISP1507 to transmit and receive USB data 9 ...
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... NXP Semiconductors Table 17. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK DATA [3:0] DIR STP NXT TX end delay (two to five clocks) Fig 13. High-speed transmit-to-transmit packet timing ISP1507E_ISP1507F_1 ...
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... NXP Semiconductors DP or DATA EOP DM CLOCK DATA [3: DIR STP NXT RX end delay (three to eight clocks) Fig 14. High-speed receive-to-transmit packet timing 9.9 Preamble Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets ...
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... NXP Semiconductors CLOCK DATA[3: Fig 15. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed or low-speed host-initiated suspend and resume Figure 16 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note that LINESTATE updates. The sequence of events for a host and a peripheral, both with ISP1507 follows. ...
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... NXP Semiconductors idle DATA [ 3:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 16. Full-speed suspend and resume 9.10.2 High-speed suspend and resume Figure 17 suspend and then initiates resume signaling. The high-speed peripheral will wake up and return to high-speed operations ...
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... NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1507 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state ...
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... NXP Semiconductors HS idle TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !squelch squelch (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OPMODE SUSPENDM !squelch squelch (01b) (00b) ...
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... NXP Semiconductors 9.10.3 Remote wake-up The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed here. In Figure 18, timing is not to scale, and not all RXCMD LINESTATE updates are shown ...
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... NXP Semiconductors LINESTATE DATA [ 3:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 3:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 18. Remote wake-up from low-power mode 9.11 No automatic SYNC and EOP generation (optional) This setting allows the link to turn off the automatic SYNC and EOP generation, and must be used for high-speed packets only ...
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... NXP Semiconductors PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE to 10b. CLOCK TXCMD ...
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... NXP Semiconductors 9.12.1 OTG charge pump A description of the charge pump is given in configured as an A-device, it can provide the V Control of the charge pump is described in 9.12.2 OTG comparators The ISP1507 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V ...
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... NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (DAT) DATA2 (SE0 Fig 20. Example of transmit followed by receive in 3-pin serial mode 9.14 Aborting transfers The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 , Section 3.8.4. ...
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... NXP Semiconductors 10. Register map Table 18. Immediate register set overview Field name VENDOR_ID_LOW VENDOR_ID_HIGH PRODUCT_ID_LOW PRODUCT_ID_HIGH FUNC_CTRL INTF_CTRL OTG_CTRL USB_INTR_EN_R_E USB_INTR_EN_F_E USB_INTR_STAT USB_INTR_L DEBUG SCRATCH Reserved (do not use) Access extended register set Vendor-specific register PWR_CTRL [1] Read (R): A register can be read. Read-only if this is the only mode given. ...
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... NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 VENDOR_ID_LOW register Table 20 Table 20. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Bit Symbol Access VENDOR_ID_ R LOW[7:0] 10.1.1.2 VENDOR_ID_HIGH register The bit description of the register is given in Table 21. VENDOR_ID_HIGH - Vendor ID High register (address R = 01h) bit description ...
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... NXP Semiconductors Table 25. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed receiver, OTG comparators and ULPI pins ...
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... NXP Semiconductors Table 26. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit allocation Bit 7 Symbol INTF_ IND_PASS PROT_DIS THRU Reset 0 Access R/W/S/C R/W/S/C Table 27. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description ...
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... NXP Semiconductors Table 28. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 Access R/W/S/C R/W/S/C Table 29. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description ...
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... NXP Semiconductors 10.1.5 USB_INTR_EN_R_E register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all transitions are enabled. Table 30. USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh, ...
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... NXP Semiconductors Table 33. USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit description Bit Symbol Description reserved 4 ID_GND_F ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND. 3 SESS_END_F Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_END ...
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... NXP Semiconductors Table 36. USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation Bit 7 Symbol reserved Reset 0 Access R Table 37. USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description Bit Symbol Description reserved - 4 ID_GND_L ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared when this register is read ...
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... NXP Semiconductors 10.1.11 Reserved Registers 19h to 2Eh are not implemented. Operating on these addresses will have no effect on the PHY. 10.1.12 Access extended register set Address 2Fh does not contain register data. Instead it links to the extended register set. The immediate register set maps to the lower end of the extended register set. ...
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... NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from V Remark: Capacitors 0.1 F and 1 F are also required by Universal Serial Bus Specification Rev. 2.0 . For details on the requirements for C ...
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... NXP Semiconductors 12. Limiting values Table 43. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current lu T storage temperature stg The ISP1507 has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0 , [1] Section 7 ...
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... NXP Semiconductors 14. Static characteristics Table 45. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter V voltage on pin REG3V3 (REG3V3) V voltage on pin REG1V8 (REG1V8) V power-on reset trip voltage POR(trip) I supply current CC I supply current on CC(I/O) pin V CC(I/O) [1] A continuous stream packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling. ...
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... NXP Semiconductors Table 46. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[3:0], RESET_N/PSW_N CC(I/O) Typical values are 3 Symbol Parameter I HIGH-level output current LOW-level output current OL I off-state output current OZ Impedance Z load impedance L Pull-up and pull-down I pull-down current pd I pull-up current ...
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... NXP Semiconductors Table 48. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter Termination V termination voltage for upstream TERM facing port pull-up Resistance R pull-up resistance on pin DP UP(DP) High-speed USB transceiver Input levels (differential receiver) V high-speed squelch detection ...
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... NXP Semiconductors Table 49. Static characteristics: charge pump CC(I/O) Typical values are 3 Symbol Parameter Voltage V output voltage on pin V O(VBUS) V leakage voltage on pin V L(VBUS) Current I output current on pin V O(VBUS) Efficiency charge pump efficiency cp Table 50. Static characteristics CC(I/O) Typical values are 3.3 V ...
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... NXP Semiconductors Table 53. Static characteristics: resistor reference CC(I/O) Typical values are 3 Symbol Parameter V output voltage on pin RREF O(RREF) 120 I CC(cp) (mA) 100 = denotes charge pump supply current. CC(cp) Fig 22. Charge pump supply current as a function of V output current BUS 5 ...
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... NXP Semiconductors 15. Dynamic characteristics Table 54. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 Symbol Parameter Reset t internal power-on reset pulse W(POR) width t REG1V8 HIGH pulse width w(REG1V8_H) t REG1V8 LOW pulse width w(REG1V8_L) t external RESET_N pulse width W(RESET_N) t regulator start-up time ...
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... NXP Semiconductors Table 55. Dynamic characteristics: digital I/O pins CC(I/O) Symbol Parameter t DATA set-up time with respect to su(DATA) the rising edge of pin CLOCK t DATA hold time with respect to h(DATA) the rising edge of pin CLOCK t DATA output delay with respect d(DATA) ...
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... NXP Semiconductors Table 56. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Symbol Parameter t driver disable delay from PHZ HIGH level t driver disable delay from PLZ LOW level t driver enable delay to PZH HIGH level t driver enable delay to PZL LOW level Receiver timing ...
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... NXP Semiconductors CONTROL IN DATA IN CONTROL OUT (DIR, NXT) DATA OUT Fig 30. ULPI timing ISP1507E_ISP1507F_1 Product data sheet CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) Rev. 01 — 28 May 2008 ISP1507E; ISP1507F ULPI HS USB OTG transceiver t , d(DIR) t d(NXT d(DIR d(DATA) d(NXT) © ...
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... NXP Semiconductors 16. Application information Table 57. Recommended bill of materials [1] Designator Application C highly recommended for bypass all applications C charge pump is used cp(C_A)-(C_B) C highly recommended for filter all applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG D recommended for all ESD ...
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V BUS USB MINI-AB GND RECEPTACLE IP4359CX4/LF SHIELD SHIELD 7 SHIELD 8 SHIELD 9 C VBUS C filter (1) Frequency is version dependent: ISP1507E: 19.2 MHz; ISP1507F: ...
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IN +3 pullup CHARGE PUMP ON V BUS USB MINI-AB GND RECEPTACLE SHIELD 6 IP4359CX4/LF SHIELD ESD SHIELD 8 SHIELD 9 (1) Frequency is ...
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pullup FAULT V BUS SWITCH OUT ON V BUS USB 3 STANDARD-A RECEPTACLE A1 A3 GND 4 IP4359CX4/LF SHIELD SHIELD 6 C VBUS C bypass (1) Frequency is version ...
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V BUS USB STANDARD-B RECEPTACLE GND SHIELD 5 IP4359CX4/ SHIELD 6 D ESD C bypass (1) Frequency is version dependent: ISP1507E: 19.2 MHz; ISP1507F: 26 MHz. Fig 34. Using the ...
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... NXP Semiconductors 17. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 60. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS NRZI ...
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... NXP Semiconductors Table 60. Acronym PLL POR RXCMD SE0 SOF SRP SYNC TTL TXCMD ULPI USB USB-IF UTMI UTMI+ 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specifi ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Recommended charge pump capacitor value .12 Table 4. ULPI signal description . . . . . . . . . . . . . . . . . .15 Table 5. Signal mapping during low-power mode . . . . .16 Table 6. Signal mapping for 3-pin serial mode . . . . . . .17 Table 7. Operating states and their corresponding resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18 Table 8. ...
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... NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN24; top view . . . . . . . . . .5 Fig 3. External capacitors connection . . . . . . . . . . . . . .10 Fig 4. Charge pump capacitor . . . . . . . . . . . . . . . . . . . .11 Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .20 Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use .22 Fig 7. Interface behavior with respect to RESET_N .23 Fig 8 ...
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... NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 ULPI controller . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 USB data serializer and deserializer 7.3 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7 7 ...
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... NXP Semiconductors 10.1 Immediate register set . . . . . . . . . . . . . . . . . . 45 10.1.1 Vendor ID and Product ID registers . . . . . . . . 45 10.1.1.1 VENDOR_ID_LOW register . . . . . . . . . . . . . . 45 10.1.1.2 VENDOR_ID_HIGH register 10.1.1.3 PRODUCT_ID_LOW register . . . . . . . . . . . . . 45 10.1.1.4 PRODUCT_ID_HIGH register . . . . . . . . . . . . 45 10.1.2 FUNC_CTRL register . . . . . . . . . . . . . . . . . . . 45 10.1.3 INTF_CTRL register . . . . . . . . . . . . . . . . . . . . 46 10.1.4 OTG_CTRL register . . . . . . . . . . . . . . . . . . . . 47 10.1.5 USB_INTR_EN_R_E register . . . . . . . . . . . . . 49 10.1.6 USB_INTR_EN_F_E register . . . . . . . . . . . . . 49 10.1.7 USB_INTR_STAT register ...