ADV7179BCP-REEL Analog Devices Inc, ADV7179BCP-REEL Datasheet
ADV7179BCP-REEL
Specifications of ADV7179BCP-REEL
Related parts for ADV7179BCP-REEL
ADV7179BCP-REEL Summary of contents
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FEATURES 1 ITU-R BT601/BT656 YCrCb to PAL/NTSC video encoder High quality 10-bit video DACs SSAF™ (super sub-alias filter) Advanced power management features CGMS (copy generation management system) WSS (wide screen signaling) 2 NTSC M, PAL N , PAL B/D/G/H/I, PAL-M ...
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ADV7174/ADV7179 TABLE OF CONTENTS Specifications ..................................................................................... 4 2.8 V Specifications ...................................................................... 4 2.8 V Timing Specifications ........................................................ 5 3.3 V Specifications ...................................................................... 6 3.3 V Timing Specifications ........................................................ 7 Absolute Maximum Ratings ............................................................ 9 ESD Caution .................................................................................. 9 Pin Configuration ...
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Appendix 3—Copy Generation Management System (CGMS) ............................................................................................................ 42 Function of CGMS Bits .............................................................. 42 Appendix 4—Wide Screen Signaling (WSS) ............................... 43 Function of WSS Bits .................................................................. 43 Appendix 5—Teletext ..................................................................... 44 Teletext Insertion......................................................................... 44 Teletext Protocol .......................................................................... 44 Appendix 6—Waveforms ...
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ADV7174/ADV7179 SPECIFICATIONS 2.8 V SPECIFICATIONS 1.235 150 Ω. All specifications T AA REF SET Table 1. Parameter STATIC PERFORMANCE 2 Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 2 ...
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V TIMING SPECIFICATIONS 1.235 150 Ω. All specifications T AA REF SET Table 2. Parameter 2, 3 MPU PORT SCLOCK Frequency SCLOCK High Pulse Width SCLOCK Low Pulse ...
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ADV7174/ADV7179 3.3 V SPECIFICATIONS 3.0 V–3 1.235 REF SET Table 3. Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High ...
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V TIMING SPECIFICATIONS 3.0 V–3 1.235 REF SET Table 4. Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulse Width SCLOCK Low Pulse Width ...
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ADV7174/ADV7179 SDATA SCLOCK CLOCK HSYNC, CONTROL FIELD/VSYNC, I/PS S BLANK PIXEL INPUT DATA HSYNC, CONTROL FIELD/VSYNC, O/PS BLANK TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating V to GND Voltage on Any Digital Input Pin GND – 0 Storage Temperature (T ) −65°C to +150°C S Junction Temperature (T ) 150°C J Lead ...
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ADV7174/ADV7179 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Input/ Mnemonic Output Function P7–P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0 the LSB. CLOCK I TTL Clock Input. Requires a stable 27 MHz reference clock ...
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GENERAL DESCRIPTION The ADV7174/ADV7179 is an integrated digital video encoder that converts digital CCIR-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with worldwide standards. The on-board SSAF (super sub-alias filter) with extended luminance frequency ...
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ADV7174/ADV7179 Table 7. Luminance Internal Filter Specifications Filter Type Filter Selection MR04 MR03 MR02 Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC Notch (PATL Extended (SSAF) CIF ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 6. Chrominance Internal Filter Specifications 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure ...
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ADV7174/ADV7179 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 12. QCIF Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 13. 1.3 MHz ...
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FREQUENCY (MHz) Figure 18. QCIF Chroma Filter 1 2 Rev Page ADV7174/ADV7179 ...
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ADV7174/ADV7179 FEATURES COLOR BAR GENERATION The ADV7174/ADV7179 can be configured to generate 100/ 7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color bars. These are enabled by setting MR17 of Mode Register 1 to Logic 1. SQUARE PIXEL MODE ...
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COMPOSITE VIDEO (e.g., VCR OR CABLE) H/LTRANSITION COUNT START LOW 128 RESERVED 13 RTC TIME SLOT: 01 NOT USED IN THE ADV7174/ADV7179 NOTES 1 F PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 PLL INCREMENT ...
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ADV7174/ADV7179 ANALOG VIDEO INPUT PIXELS Y NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE DISPLAY 522 523 524 525 DISPLAY 260 261 262 263 264 H V ODD FIELD F EAV CODE ...
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DISPLAY 622 623 624 625 EVEN FIELD ODD FIELD F DISPLAY 309 310 311 312 313 H V ODD FIELD EVEN FIELD F ANALOG VIDEO Figure 23. Timing Mode 0 Data Transitions (Master Mode) ...
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ADV7174/ADV7179 Mode 1: Slave Option HSYNC , BLANK , FIELD (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD ...
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Mode 1: Master Option HSYNC , BLANK , FIELD (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD ...
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ADV7174/ADV7179 Mode 2: Slave Option HSYNC , VSYNC , BLANK (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 accepts horizontal and vertical SYNC signals. A coincident low transition of both ...
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Mode 2: Master Option HSYNC , VSYNC , BLANK (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 can generate horizontal and vertical SYNC signals. A coincident low transition of both ...
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ADV7174/ADV7179 Mode 3: Master/Slave Option HSYNC , BLANK , FIELD (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 accepts or generates ...
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POWER-ON RESET After power-up necessary to execute a reset operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port so that the pixel inputs, P7–P0, are selected. ...
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ADV7174/ADV7179 Frequency Registers 1, 2, and 3. The subcarrier frequency registers should not be accessed independently. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal ...
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REGISTER PROGRAMMING This section describes the configuration of each register, including the subaddress register, mode registers, subcarrier frequency registers, the subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, and NTSC pedestal control registers. SUBADDRESS ...
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ADV7174/ADV7179 MODE REGISTER 0 (MR0) Bits: MR07 – MR00 Address: SR4–SR0 = 00H Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to. MR07 CHROMA FILTER ...
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MODE REGISTER 1 (MR1) Bits: MR17–MR10 Address: SR4–SR0 = 01H Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to. MR17 DAC A CONTROL MR16 0 ...
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ADV7174/ADV7179 MODE REGISTER 2 (MR2) Bits: MR27–MR20 Address: SR4–SR0 = 02H Mode Register 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can be read from as well as ...
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MODE REGISTER 3 (MR3) Bits: MR37–MR30 Address: SR4–SR0 = 03H Mode Register 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3. MR37 TTXREQ BIT MODE CONTROL MR36 0 1 INPUT DEFAULT ...
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ADV7174/ADV7179 MODE REGISTER 4 (MR4) Bits: MR47–MR40 Address: SR4–SR0 = 04H Mode Register 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4. MR47 MR46 SLEEP MODE CONTROL MR46 0 DISABLE 1 ...
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TIMING MODE REGISTER 0 (TR0) Bits: TR07–TR00 Address: SR4–SR0 = 07H Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. TR07 TIMING REGISTER RESET TR07 ...
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ADV7174/ADV7179 TIMING MODE REGISTER 1 (TR1) Bits: TR17–TR10 Address: SR4–SR0 = 08H Timing Register 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register can be read from as well ...
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SUBCARRIER FREQUENCY REGISTERS 3–0 Bits: FSC3–FSC0 Address: SR4–SR00 = 09H–0CH These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation: No. of Subcarrie r Frequency Values No. ...
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ADV7174/ADV7179 CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0 Bits: CCD15–CCD0 Subaddress: SR4–SR0 = 10H–11H These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes are ...
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TELETEXT REQUEST CONTROL REGISTER (TC07) Bits: TC07–TC00 Address: SR4–SR0 = 19H Teletext control register is an 8-bit-wide register (see Figure 50). Table 17. Teletext Request Control Register Bit Name Bit No. TTXREQ Rising Edge Control TC07–TC04 TTXREQ Falling Edge Control ...
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ADV7174/ADV7179 CGMS_WSS REGISTER 1 (C/W1) Bits: C/W17–C/W10 Address : SR4–SR0 = 17H CGMS_WSS Register 8-bit-wide register. Figure 52 shows the operations under the control of this register. C/W17 C/W17 – C/W16 CGMS DATA BITS Table 19. C/W1 ...
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APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7174/ADV7179 is a highly integrated circuit contain- ing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the ...
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ADV7174/ADV7179 SUPPLY DECOUPLING For optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 μF ceramic capacitor decoupling. Each group of V ...
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APPENDIX 2—CLOSED CAPTIONING The ADV7174/ADV7179 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of ...
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ADV7174/ADV7179 APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7174/ADV7179 supports the CGMS, conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and on Line 283 of the even fields. Bits C/W05 and C/W06 control ...
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APPENDIX 4—WIDE SCREEN SIGNALING (WSS) The ADV7174/ADV7179 supports WSS, conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7174/ ADV7179 is configured in PAL mode. The WSS data is 14 ...
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ADV7174/ADV7179 APPENDIX 5—TELETEXT TELETEXT INSERTION t is the time needed by the ADV7174/ADV7179 to interpolate PD input data on TTX and insert it onto the CVBS or Y outputs, such that it appears t = 10.2 μs after the leading ...
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APPENDIX 6—WAVEFORMS NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 963.8mV 286mV (p-p) 650mV 335.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE 714.2mV Figure ...
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ADV7174/ADV7179 NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mV (p-p) 650mV 299.3mV 0mV 100 IRE 0 IRE –40 IRE 714.2mV BLANK/BLACK LEVEL Figure 65. NTSC Composite Video Levels ...
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PAL WAVEFORMS 1288.6mV 1051mV 351mV 51mV 1051mV 351mV 51mV 989.7mV 300mV (p-p) 650mV 317.7mV 0mV 1051mV 351mV 51mV 700mV Figure 69. PAL Composite Video Levels 700mV Figure 70. PAL Luma Video Levels 672mV (p-p) Figure 71. PAL Chroma Video Levels ...
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ADV7174/ADV7179 Pb Pr WAVEFORMS +334mV +171mV BETACAM LEVEL 0mV –171mV –334mV –05mV Figure 73. NTSC 100% Color Bars, No Pedestal Pb Levels +309mV +158mV BETACAM LEVEL 0mV –158mV –309mV –467mV Figure 74. NTSC 100% Color Bars with Pedestal Pb Levels ...
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APPENDIX 7—OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, chroma, and RGB outputs of the ADV7174/ADV7179, the filter shown in Figure 79 can be used. Plots of the filter characteristics are shown in Figure ...
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ADV7174/ADV7179 APPENDIX 8—RECOMMENDED REGISTER VALUES The ADV7174/ADV7179 registers can be set depending on the user standard required. The power-on reset values can be found in Figure 37. The following examples give the various register formats for several video standards. In ...
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Table 26. PAL- 4.43361875 MHz) SC Address Description 00H Mode Register 0 01H Mode Register 1 02H Mode Register 2 03H Mode Register 3 04H Mode Register 4 07H Timing Register 0 08H Timing Register 1 09H Subcarrier ...
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... ADV7179KCP-REEL 0°C to 70°C 2 ADV7179KCPZ 0°C to 70°C 2 ADV7179KCPZ-REEL 0°C to 70°C 1 ADV7179BCP −40°C to +85°C 1 ADV7179BCP-REEL −40°C to +85°C 2 ADV7179BCPZ −40°C to +85°C 2 ADV7179BCPZ-REEL −40°C to +85° ADV7179WBCPZ −40°C to +85° ADV7179WBCPZ–REEL −40°C to +85°C ...