AD1847JP

Manufacturer Part NumberAD1847JP
ManufacturerAnalog Devices Inc
AD1847JP datasheet
 


Specifications of AD1847JP

Single Supply Voltage (typ)5VSingle Supply Voltage (min)4.75V
Single Supply Voltage (max)5.25VPackage TypePLCC
Lead Free Status / RoHS StatusNot Compliant  
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FEATURES
Single-Chip Integrated
Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSP
PRODUCT OVERVIEW
®
The AD1847 SoundPort
Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multi-
media applications requiring operation from a single +5 V sup-
ply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
ANALOG
ANALOG
SUPPLY
I/O
L
LINE 1
INPUT
R
L
LINE 2
INPUT
R
L
AUX 1
INPUT
R
GAIN/ATTEN/MUTE
L
L
LINE
R
OUTPUT
R
GAIN/ATTEN
L
/MUTE
AUX 2
INPUT
GAIN/ATTEN
R
/MUTE
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
I
S
A
B
U
S
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of
verters (ADCs) and a stereo pair of
verters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs’ output can be digitally
mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a se-
rial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit -law or A-law
companded digital data.
FUNCTIONAL BLOCK DIAGRAM
CLOCK
DIGITAL
CRYSTALS
OUT
SUPPLY
2
OSCILLATORS
M
L
A/D
GAIN
U
CONVERTER
X
R
A/D
GAIN
CONVERTER
ATTEN/
D/A
ATTEN
CONVERTER
MUTE
ATTEN/
D/A
ATTEN
CONVERTER
MUTE
REFERENCE
2.25V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Serial-Port 16-Bit
SoundPort Stereo Codec
AD1847
ASIC
DSP
Figure 1. Example System Diagram
analog-to-digital con-
digital-to-analog con-
(Continued on page 7)
DIGITAL
I/O
2
RESET
POWER
DOWN
/A
BUS
LAW
MASTER
S
TIME SLOT
/A
E
LAW
INPUT
R
TIME SLOT
I
OUTPUT
A
SERIAL DATA
ATTEN
L
OUTPUT
SERIAL DATA
P
INPUT
O
/A
2
LAW
R
EXTERNAL
T
CONTROL
/A
LAW
SERIAL BIT
CLOCK
FRAME
SYNC
AD1847
® Analog Devices, Inc., 1996
AD1847
Fax: 617/326-8703

AD1847JP Summary of contents

  • Page 1

    FEATURES Single-Chip Integrated Digital Audio Stereo Codec Supports the Microsoft Windows Sound System* Multiple Channels of Stereo Input Analog and Digital Signal Mixing Programmable Gain and Attenuation On-Chip Signal Filters Digital Interpolation and Decimation Analog Output Low-Pass Sample Rates ...

  • Page 2

    AD1847–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1007 Analog Output Passband 20 FFT Size 4096 V 2.4 IH ...

  • Page 3

    ANALOG-TO-DIGITAL CONVERTERS Resolution Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) THD+N (Referenced to Full Scale) Signal-to-Intermodulation Distortion† ADC Crosstalk† Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line1 to Line2 ...

  • Page 4

    AD1847 SYSTEM SPECIFICATIONS System Frequency Response† (Line In to Line Out kHz) Differential Nonlinearity† Phase Linearity Deviation† STATIC DIGITAL SPECIFICATIONS High Level Input Voltage ( Digital Inputs XTAL1/2I Low Level Input Voltage (V ) ...

  • Page 5

    ... TSO 7 TSI GNDD 10 RESET 11 AD1847JP PWRDOWN 12 Top View (Not to Scale GNDA REFI V 16 REF R_LINE1 N CONNECT REV. B Units Model V AD1847JP V AD1847JST *P = PLCC TQFP. 10.0 mA +70 C +150 C PINOUTS GNDD TSO 37 XCTL1 36 XCTL0 35 GNDD GNDD RESET PWRDOWN L_AUX2 GNDA V 31 R_AUX2 V 30 ...

  • Page 6

    AD1847 PIN DESCRIPTIONS Parallel Interface Pin Name PLCC TQFP I/O SCLK 1 39 I/O SDFS 6 44 I/O SDI SDO RESET PWRDOWN TSO 7 ...

  • Page 7

    Miscellaneous Pin Name PLCC TQFP I/O XTAL1I XTAL1O XTAL2I XTAL2O XCTL1:O 37 & & REF REFI ...

  • Page 8

    AD1847 Changes in DAC output attenuation take effect only on zero crossings of the digital signal, thereby eliminating “zipper” noise on playback. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guar- antees that ...

  • Page 9

    CONTROL REGISTERS Control Register Mapping The AD1847 has six 16-bit and thirteen 8-bit on-chip user- accessible control registers. Control information is sent to the AD1847 in the 16-bit Control Word. Status information is sent from the AD1847 in the 16-bit ...

  • Page 10

    AD1847 Control Word (16-Bit) Data 15 Data 14 Data 13 CLOR MCE Data 7 Data 6 DATA7 DATA6 DATA5 DATA7:0 Index Register Data. These bits are the data for the desired AD1847 Index Register referenced by the Index Address. Written ...

  • Page 11

    Status Word (16-Bit) Data 15 Data 14 res res Data 7 Data 6 res res INIT Initialization. This bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is ...

  • Page 12

    AD1847 Index Readback (16-Bit) Data 15 Data 14 CLOR MCE Data 7 Data 6 DATA7 DATA6 DATA7:0 Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index Address from the previous ...

  • Page 13

    Left Input Control Register (Index Address 0) IA3:0 Data 7 Data 6 0000 LSS1 LSS0 LIG3:0 Left Input Gain Select. The least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is +22.5 dB. res Reserved for ...

  • Page 14

    AD1847 Left Auxiliary #2 Input Control Register (Index Address 4) IA3:0 Data 7 Data 6 0100 LMX2 res LX2G4:0 Left Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB. LX2G4 produces ...

  • Page 15

    Data Format Register (Index Address 8) IA3:0 Data 7 Data 6 1000 res FMT The contents of this register can NOT be changed except when the AD1847 is in the Mode Change Enable (MCE) state (i.e., the MCE bit in ...

  • Page 16

    AD1847 Interface Configuration Register (Index Address 9) IA3:0 Data 7 Data 6 1001 res res PEN Playback Enable. This bit will enable the playback of data in the format selected. PEN may be set and reset without setting the MCE ...

  • Page 17

    Miscellaneous Information Register (Index Address 12) IA3:0 Data 7 Data 6 1100 FRS TSSEL The Miscellaneous Information Register can only be changed when the AD1847 is in the Mode Change Enable (MCE) state. Changes to this register are updated at ...

  • Page 18

    AD1847 Serial Data Interface The AD1847 serial data interface uses a Time Division Multi- plex (TDM) scheme that is compatible with DSP serial ports configured in Multi-Channel Mode with either 16-bit time slots. An AD1847 is always ...

  • Page 19

    Control Word Data 15 Data 14 CLOR MCE Data 7 Data 6 DATA7 DATA6 Left Playback Data Data 15 Data 14 DATA15 DATA14 Data 7 Data 6 DATA7 DATA6 Right Playback Data Data 15 Data 14 DATA15 DATA14 Data 7 ...

  • Page 20

    AD1847 IA3:0 Data 7 Data 6 0000 LSS1 LSS0 0001 RSS1 RSS0 0010 LMX1 res 0011 RMX1 res 0100 LMX2 res 0101 RMX2 res 0110 LDM res 0111 RDM res 1000 res FMT 1001 res res 1010 XCTL1 XCTL0 1011 ...

  • Page 21

    MHz 2 XTAL1I,O XTAL2I,O SCLK SDFS AD1847 SDI (MASTER) SDO TSO CLKOUT TSI XTAL2I SCLK XTAL1O SDFS XTAL2O SDI (SLAVE 1) SDO TSO XTAL1I TSI XTAL2I SCLK XTAL1O XTAL2O N/C SDFS SDI (SLAVE 2) SDO TSO XTAL1I Figure ...

  • Page 22

    AD1847 When the AD1847 is in bus slave mode (BM = LO), the TSI pin should be connected to the TSO pin of the AD1847 master or slave which has been assigned to the preceding time slots. The signal on ...

  • Page 23

    DATA FORMAT DEFINITIONS There are four data formats supported by the AD1847: 16-bit signed, 8-bit unsigned, 8-bit companded -law, and 8-bit com- panded A-law. The AD1847 supports these four formats because each of them have found wide use in important ...

  • Page 24

    AD1847 Circuits for 2 V line-level inputs and auxiliaries are shown in rms Figure 14 and Figure 15. Note that these are divide-by-two resistive dividers. The input resistor and 560 pF (1000 pF) capacitor provide the single-pole of antialias filtering ...

  • Page 25

    The crystals shown in the crystal connection circuitry of Figure 21 should be fundamental-mode and parallel-tuned. Two sources for the exact crystals specified are Component Market- ing Services in Massachusetts, U.S. at 617/762-4339 and Cardinal Components in New Jersey, U.S. ...

  • Page 26

    AD1847 FREQUENCY RESPONSE PLOTS 10 0 –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SAMPLE FREQUENCY – F Figure 24. AD1847 Analog-to-Digital Frequency Response (Full-Scale Line-Level Inputs, 0 ...

  • Page 27

    SCLK SDFS PD1 H BIT 15 BIT 14 SDI t DV SDO BIT 14 BIT 15 Figure 28. Time Slot Timing Diagram SCLK SDFS t PD1 SDI SDO LAST VALID TIME SLOT ...

  • Page 28

    AD1847 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead PLCC (P-44A) 0.048 (1.21) 0.056 (1.42) 0.042 (1.07) 0.042 (1.07 PIN 1 39 IDENTIFIER 0.048 (1.21) 0.042 (1.07) TOP VIEW 0.020 0.656 (16.66) ...