AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 15

• Manufacturer Part Number: AD1847JP
• Manufacturer: Analog Devices Inc

Specifications of AD1847JP

• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PLCC
• Lead Free Status / RoHS Status: Not Compliant

REV. B
Data Format Register (Index Address 8)
The contents of this register can NOT be changed except when the AD1847 is in the Mode Change Enable (MCE) state (i.e., the MCE bit in
the Control Word is HI). Write attempts to this register when the AD1847 is not in the MCE state will not be successful.
CSL
CFS2:0
S/M
C/L
FMT
This register’s initial state after reset is: 0000 0000 (00h).
res
IA3:0
1000
Clock Source Select. This bit selects the clock source to be used for the audio sample rate.
0
1
Clock Frequency Divide Select. These bits select the audio sample rate frequency. The audio sample rate depends on
which clock source is selected and the frequency of the clock source.
Note that the AD1847’s internal oscillators can be overdriven by external clock sources at the crystal inputs. This is the
configuration used by serial bus slave codecs in daisy-chained multiple codec systems. If an external clock source is ap-
plied, it will be divided down by the selected Divide Factor. The external clock need not be at the recommended crystal
frequencies.
Stereo/Mono Select. This bit determines how the audio data streams are formatted. Selecting stereo will result with alter-
nating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels.
Mono capture only captures data from the left audio channel.
0
1
Companded/Linear Select. This bit selects between a linear digital representation of the audio signal or a nonlinear, com-
panded format for all input and output data. The type of linear PCM or the type of companded format is defined by the
FMT bits.
0
1
Format Select. This bit defines the format for all digital audio input and output based on the state of the C/L bit.
Reserved for future expansion. Write zeros (LO) to all reserved bits.
Data 7
XTAL1 (24.576 MHz)
XTAL2 (16.9344 MHz)
Mono
Stereo
Linear PCM
Companded
res
CFS2:0
0
1
2
3
4
5
6
7
0
1
Data 6
FMT
Linear PCM (C/L = 0)
8-bit unsigned linear PCM
16-bit signed linear PCM
Divide
Factor
3072
1536
896
768
448
384
512
2560
Data 5
C/L
24.576 MHz
8.0 kHz
16.0 kHz
27.42857 kHz
32.0 kHz
Not Supported
Not Supported
48.0 kHz
9.6 kHz
XTAL1
Data 4
S/M
–15–
Companded (C/L = 1)
8-bit -law companded
8-bit A-law companded
Data 3
CFS2
XTAL2
16.9344 MHz
5.5125 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.615 kHz
Data 2
CFS1
Data 1
CFS0
Data 0
AD1847
CSL