AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 16

• Manufacturer Part Number: AD1847JP
• Manufacturer: Analog Devices Inc

Specifications of AD1847JP

• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PLCC
• Lead Free Status / RoHS Status: Not Compliant

AD1847
Interface Configuration Register (Index Address 9)
PEN
ACAL
res
This register’s initial state after reset is: 0000 1000 (08h).
Pin Control Register (Index Address 10)
CLKTS Clock Three-State. If the BM bit is HI, and the CLKTS bit is HI, then the CLKOUT pin will be three-stated. If the BM
XCTL1:0 External Control. The state of these independent bits is reflected on the respective XCTL1 and XCTL0 pins of the
res
This register’s initial state after reset is: 0000 0000 (00h).
Invalid Address (Index Address 11)
inval
IA3:0
IA3:0
IA3:0
1001
1010
1011
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
Playback Enable. This bit will enable the playback of data in the format selected. PEN may be set and reset without
setting the MCE bit.
0
1
Autocalibrate Enable. This bit determines whether the AD1847 performs an autocalibrate when exiting from the Mode
Change Enable (MCE) state. If the ACAL bit is not set, the previous autocalibration values are used when returning from
the Mode Change Enable (MCE) state and no autocalibration takes place. Autocalibration must be preformed after initial
power-up for proper operation. This bit is HI after reset.
0
1
NOTE: The ACAL bit can only be changed when the AD1847 is in the Mode Change Enable (MCE) state.
Reserved for future expansion. Write zeros (LO) to all reserved bits.
bit is HI, and the bit CLKTS is LO, then the CLKOUT pin is not three-stated. If the BM bit is LO, then the CLKOUT
pin is always three-stated.
AD1847.
0
1
Reserved for future expansion. Write zeros (LO) to all reserved bits.
XCTL1
Data 7
Data 7
Data 7
inval
Playback Disabled
Playback Enabled
No autocalibration
Autocalibration allowed
TTL logic LO on XCTL1, XCTL0 pins
TTL logic HI on XCTL1, XCTL0 pins
res
XCTL0
Data 6
Data 6
Data 6
inval
res
CLKTS
Data 5
Data 5
Data 5
inval
res
Data 4
Data 4
Data 4
inval
res
res
–16–
Data 3
Data 3
Data 3
ACAL
inval
res
Data 2
Data 2
Data 2
inval
res
res
Data 1
Data 1
Data 1
inval
res
res
Data 0
Data 0
Data 0
PEN
inval
res
REV. B