AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 18

• Manufacturer Part Number: AD1847JP
• Manufacturer: Analog Devices Inc

Specifications of AD1847JP

• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PLCC
• Lead Free Status / RoHS Status: Not Compliant

AD1847
Serial Data Interface
The AD1847 serial data interface uses a Time Division Multi-
plex (TDM) scheme that is compatible with DSP serial ports
configured in Multi-Channel Mode with either 32 or 16 16-bit
time slots. An AD1847 is always the serial bus master, transmit-
ting the serial clock (SCLK) and the serial data frame sync
(SDFS). The AD1847 always receives control and playback
data in time slots 0, 1 and 2. The AD1847 will transmit status
or index register readback and capture data in time slots 0, 1
and 2 if TSSEL = 1, and will transmit status or index register
readback and capture data in time slots 3, 4 and 5 if TSSEL =
0. The following table in Figure 7 shows an example of how the
time slots might be assigned.
In this example design, which uses the ADSP-21xx DSP, each
frame is divided into 32 time slots of 16-bits each (FRS = 0).
Two audio samples are contained in the 32 time slots, with a
single frame sync (SDFS) at the beginning of the frame. The
ADSP-21xx serial port (SPORT0) supports 32 time slots. The
format of the first 16 time slots (sample N) is the same as the
format of the second 16 time slots (sample N+1). In this ex-
ample, 24 time slots are used, as indicated below. Note that
time slots 12 through 15 and 28 through 31 are unused in this
example, and that Figure 7 presumes that TSSEL = 0 (“1-wire”
system).
Slot Number Source
0, 16
1, 17
2, 18
3, 19
4, 20
5, 21
0, 16
1, 17
2, 18
3, 19
4, 20
5, 21
6, 22
7, 23
8, 24
9, 25
10, 26
11, 27
Figure 7. Time Slot Assignment Example
ASIC
AD1847
DSP
AD1847
ASIC
DSP
Destination Format
AD1847
ASIC
AD1847
DSP
DSP
ASIC
AD1847 Control Word
Left Playback Data
Right Playback Data
AD1847 Status Word/
Index Readback
Left Capture Data
Right Capture Data
AD1847 Control Word
Left Playback Data
Right Playback Data
AD1847 Status Word/
Index Readback
Left Capture Data
Right Capture Data
DSP Control
Left Processed
Playback Data
Right Processed
Playback Data
DSP Status
Left Processed
Capture Data
Right Processed
Capture Data
–18–
Note that in this “1-wire” system example, the Digital Signal
Processor (DSP) and ISA Bus Interface ASIC (ASIC) use the
same slots to communicate to the AD1847. This reduces the
number of total time slots required and eliminates the need for
the AD1847 to distinguish between DSP data and ASIC data.
Also, in this example the ASIC and the DSP do not send data to
the AD1847 at the same time, so separate slots are unnecessary.
The digital data in the serial interface is pipelined up to 2
samples deep. This pipelining is required to properly resolve the
interface between the relatively fast fixed SCLK rate, and the
relatively slow sample rates (and therefore frame sync rates) at
which the AD1847 is capable of running. At low sample rates,
two samples of data can be serviced in a fraction of a sample pe-
riod. For example, at an 8 kHz sample rate, 32 time slots only
consume 32
period. The two-deep data pipeline thus allows sample overrun
(capture) and sample underrun (playback) to be avoided.
Figure 8 represents a logical view of the slot utilization between
devices.
Note that this is a system specific 1-wire example. For non-DSP
operation, the DSP is either not present or disabled. If the DSP
is present, the ASIC configures the DSP through slot 6 (and slot
22) to three-state its outputs in time slots 0, 1 and 2 (and slots
16, 17 and 18). The ASIC can then enable its drivers for time
slots 0, 1 and 2 (and slots 16, 17 and 18). For DSP operation,
the ASIC three-states its outputs for time slots 0, 1 and 2 (and
slots 16, 17 and 18) and enables the DSP drivers for slots 0, 1
and 2 (and slots 16, 17, and 18).
An application note is available from Analog Devices with addi-
tional information on interfacing to the AD1847 serial port.
This application note can be obtained through your local Ana-
log Devices representative, or downloaded from the DSP Bulle-
tin Board Service at [phone] (8 data bits, no parity, 1
stop bit, 300/1200/2400/4600 baud).
25, 26, 27
9, 10, 11,
NOTE: DSP MUST HAVE TWO SERIAL PORTS
ASIC
Figure 8. Time Slot Allocation Example
22, 23, 24
6, 7, 8,
16
(1/12.288 MHz) = 41.67 s out of a 125 s
0, 1, 2, 16, 17, 18
3, 4, 5, 19, 20, 21
DR
DT
ADSP-21XX
16, 17, 18
0, 1, 2,
DT
DR
19, 20, 21
3, 4, 5,
SDI
SDO
AD1847
REV. B