XC5VLX50T-2FFG665C Xilinx Inc, XC5VLX50T-2FFG665C Datasheet - Page 29

FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA

XC5VLX50T-2FFG665C

Manufacturer Part Number
XC5VLX50T-2FFG665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665C

Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-2FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-2FFG665C
Manufacturer:
XILINX
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Quantity:
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Table 52: Register-to-Register Performance (Cont’d)
Table 53: Interface Performances
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Notes:
1.
2.
3.
4.
5.
6.
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter
DSP48E Dual 24-bit Adder/Subtracter
DSP48E 48-bit Adder/Subtracter
DSP48E 48-bit Counter
DSP48E 48-bit Comparator
DSP48E 25 x 18 bit Pipelined Multiplier
DSP48E Direct 4-tap FIR Filter Pipelined
DSP48E Systolic n-tap FIR Filter Pipelined
Networking Applications
SFI-4.1 (SDR LVDS Interface)
SPI-4.2 (DDR LVDS Interface)
Memory Interfaces
DDR
DDR2
QDR II SRAM
RLDRAM II
Device used is the XC5VLX50T- FF1136
Performance defined using design implementation described in application note XAPP856: SFI-4.1 16-Channel SDR Interface with Bus
Alignment
Performance defined using design implementation described in application note XAPP860: 16-Channel, DDR LVDS Interface with Real-time
Window Monitoring
Performance defined using design implementation described in application note XAPP851: DDR SDRAM Controller
Performance defined using design implementation described in application note XAPP858: High-Performance DDR2 SDRAM Interface Data
Capture
Performance defined using design implementation described in application note XAPP853: QDRII SRAM Interface
Performance defined using design implementation described in application note XAPP852: Synthesizable RLDRAM II Controller
(3)
(4)
(6)
(5)
Description
Description
(1)
(2)
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
1.25 Gb/s
710 MHz
200 MHz
333 MHz
300 MHz
333 MHz
-3
550
550
550
550
550
550
510
550
-3
Register-to-Register (with I/O Delays)
Speed Grade
Speed Grade
1.25 Gb/s
710 MHz
200 MHz
300 MHz
300 MHz
300 MHz
500
500
500
500
500
500
458
500
-2
-2
450
450
450
450
450
450
397
450
-1
645 MHz
200 MHz
267 MHz
250 MHz
250 MHz
1.0 Gb/s
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
29

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