AD9852ASQ Analog Devices Inc, AD9852ASQ Datasheet

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AD9852ASQ

Manufacturer Part Number
AD9852ASQ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9852ASQ

Lead Free Status / RoHS Status
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INTERNAL/EXTERNAL
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance:
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and shaped
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
I/O UPDATE CLOCK
on/off keying function
frequency HOLD function
80 dB SFDR at 100 MHz (±1 MHz) A
FSK/BPSK/HOLD
BIDIRECTIONAL
REFERENCE
DIFF/SINGLE
CLOCK IN
SELECT
DATA IN
SYSTEM
CLOCK
SYSTEM
CLOCK
REFCLK
BUFFER
2
MODE SELECT
FREQUENCY
INT
3
DELTA
WORD
EXT
48
CLK
D
FREQUENCY
RATE TIMER
MUX
MULTIPLIER
4× TO 20×
DELTA
SYSTEM
REFCLK
Q
CLOCK
OUT
PROGRAMMABLE
FREQUENCY
UPDATE CLOCK
TUNING
WORD 1
INTERNAL
SYSTEM CLOCK
MUX
÷2
48
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY
48
WORD 2
TUNING
SYSTEM
CLOCK
MUX
48
48
48
PROGRAMMING REGISTERS
PHASE/OFFSET
FIRST 14-BIT
READ
Figure 1.
DDS CORE
17
WORD
MUX
AD9852
14
14
WRITE
CMOS 300 MSPS Complete DDS
17
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
SIN(x)/x correction
Simplified control interface
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small 80-lead LQFP packaging
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
10 MHz serial 2-wire or 3-wire SPI®-compatible, or
100 MHz parallel 8-bit programming
PHASE/OFFSET
SECOND 14-BIT
PARALLEL
Q
SERIAL/
SELECT
I
SYSTEM
CLOCK
WORD
12
14
FILTER
SINC
INV.
I/O PORT BUFFERS
PROGRAMMING
6-BIT ADDRESS
OR SERIAL
MODULATION
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
LINES
DIGITAL MULTIPLIERS
12
AM
©2005 Analog Devices, Inc. All rights reserved.
BUS
CONTROL
12-BIT DC
SYSTEM
CLOCK
PARALLEL
LOAD
8-BIT
12
12
CONTROL
COMPARATOR
COSINE
12-BIT
DAC
12-BIT
DAC
MASTER
RESET
AD9852
www.analog.com
DAC R
CLOCK
OUT
OSK
GND
+V
ANALOG
OUT
ANALOG
OUT
ANALOG
IN
S
SET

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AD9852ASQ Summary of contents

Page 1

FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit D/A converters Ultrahigh speed comparator rms jitter Excellent dynamic performance SFDR at 100 MHz (±1 MHz) A OUT 4× to 20× ...

Page 2

AD9852 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Overview........................................................................................ 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 9 Explanation of Test Levels ........................................................... 9 ESD Caution.................................................................................. 9 Pin ...

Page 3

REVISION HISTORY 12/05—Rev Rev. D Updated Format.................................................................. Universal Changes to General Description .....................................................4 Changes to Explanation of Test Levels Section .............................9 Change to Pin Configuration ........................................................10 Changes to Figure 65 ......................................................................47 Changes to Outline Dimensions ...................................................52 Changes to ...

Page 4

AD9852 GENERAL DESCRIPTION The AD9852 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable agile synthesizer function. When referenced to an accurate ...

Page 5

... SPECIFICATIONS V = 3.3 V ± 5 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASQ, S SET external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852AST, unless otherwise noted. Table 1. Parameter 1 REF CLOCK INPUT CHARACTERISTICS ...

Page 6

... Logic 0 Voltage, High Z Load Output Power, 50 Ω Load, 120 MHz Toggle Rate Propagation Delay 6 Output Duty Cycle Error Rise/Fall Time Load Toggle Rate, High Z Load Toggle Rate, 50 Ω Load 7 Output Cycle-to-Cycle Jitter AD9852ASQ Test Temp Level Min Typ Max 25°C V 140 25° ...

Page 7

... Data Clock Pulse Width High) SCLKPWH T (Serial Data Clock Pulse Width Low) SCLKPWL T (Serial Data Hold Time) DHLD T (Data Valid Time CMOS LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance AD9852ASQ Test Temp Level Min Typ Max 25° 25° 25° 25° 25° ...

Page 8

... LQFP, can cause the maximum die junction temperature of 150° exceeded. Refer to the Power Dissipation and Thermal Considerations section for derating and thermal management information. 11 All functions engaged. 12 All functions except inverse sinc engaged. 13 All functions except inverse sinc and digital multipliers engaged. AD9852ASQ Test Temp Level Min Typ Max 25°C ...

Page 9

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature V S Digital Inputs Digital Output Current Storage Temperature Operating Temperature Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASQ) Maximum Clock Frequency (AST) θ (ASQ) JA θ (ASQ) JC θ ...

Page 10

AD9852 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD DVDD DGND DGND A2/IO RESET A1/SDO A0/SDIO I/O UD CLK CONNECT Table 4. Pin Function Descriptions Pin Number ...

Page 11

Pin Number Mnemonic 19 A0/SDIO 20 I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK 31, 32, 37, 38, 44, 50, 54, AVDD 60, 65 33, 34, 39, 40, 41, 45, 46, AGND 47, 53, 59, 62, 66, ...

Page 12

AD9852 AVDD I I OUT OUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC Outputs B. Comparator Output AVDD VINP/ VINN COMPARATOR OUT C. Comparator Input Figure 3. Equivalent Input and Output ...

Page 13

TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9852 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10. Each graph is plotted from 0 ...

Page 14

AD9852 Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise, and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. ...

Page 15

Figure 18 and Figure 19 shows the narrow-band performance of the AD9852 when operating with a 30 MHz reference clock with the REFCLK multiplier enabled at 10× vs. a 300 MHz reference clock with the REFCLK multiplier bypassed. 0 –10 ...

Page 16

AD9852 RISE TIME 1.04ns –33ps 0ps 500ps/DIV 232mV/DIV Figure 22. Typical Comparator Output Jitter, 40 MHz A with REFCLK Multiplier Bypassed CH1 500mVΩ M 500ps CH1 Figure 23. Comparator Rise/Fall Times JITTER [10.6ps RMS] +33ps 50Ω INPUT , 300 MHz ...

Page 17

TYPICAL APPLICATIONS VCA REFERENCE RF/IF INPUT LOW-PASS COS REFCLK FILTER AD9852 Figure 25. Synthesized LO Application for the AD9852 I 8 I/Q MIXER DUAL AND 8-/10-BIT LOW-PASS Q 8 ADC FILTER ADC CLOCK FREQUENCY LOCKED TO Tx ...

Page 18

AD9852 REFERENCE CLOCK REFERENCE Figure 30. Differential Output Connection for Reduction of Common-Mode Signals AD9852 8-BIT PARALLEL OR μPROCESSOR/ SERIAL PROGRAMMING CONTROLLER DATA AND CONTROL FPGA, ETC. SIGNALS 300MHz MAX DIRECT MODE OR 15MHz TO 75MHz REFERENCE CLOCK MAX IN ...

Page 19

MODES OF OPERATION There are five programmable modes of operation of the AD9852. Selecting a mode requires that three bits in the control register (Parallel Address 1F hex) be programmed as shown in Table 5. Table 5. Mode Selection Table ...

Page 20

AD9852 Table 6. Function Availability vs. Mode of Operation Function Phase Adjust 1 Phase Adjust 2 Single-Pin FSK/BPSK or HOLD Single-Pin Shaped Keying Phase Offset or Modulation Amplitude Control or Modulation Inverse Sinc Filter Frequency Tuning Word 1 Frequency Tuning ...

Page 21

F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 TW2 DFW I/O UD CLK FSK DATA (PIN 29) F2 FREQUENCY F1 0 000 (DEFAULT) MODE TW1 0 0 TW2 I/O UD CLK FSK DATA The purpose of ramped FSK is to ...

Page 22

AD9852 Figure 35. The ramp rate clock determines the amount of time spent at each intermediate frequency between F1 and F2. The counter stops automatically when the destination frequency is achieved. The dwell time spent at F1 and F2 is ...

Page 23

Additional flexibility in the ramped FSK mode is provided by the AD9852’s ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp-rate counter at any time during the ramping from vice ...

Page 24

AD9852 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 DFW RAMP RATE I/O UD CLK Basic FM Chirp Programming Steps 1. Program a start frequency into Frequency Tuning Word 1 (Parallel Register Address 4 hex to Parallel Register Address 9 ...

Page 25

Shown in the diagram is the I/O update clock, which is either user-supplied or internally generated. See the Internal and External Update Clock section for a discussion of the I/O update. Next, the CLR ACC2 control bit (Register Address 1F ...

Page 26

AD9852 FREQUENCY F1 0 000 (DEFAULT) MODE TW1 0 DFW RAMP RATE HOLD I/O UD CLK The 32-bit automatic I/O update counter can be used to construct complex chirp or ramped FSK sequences. Because this internal counter is synchronized with ...

Page 27

PHASE 0 MODE 000 (DEFAULT) FTW1 0 PHASE ADJUST 1 PHASE ADJUST 2 BPSK DATA I/O UD CLK 100 (BPSK) F1 270° 90° Figure 45. BPSK Mode Rev Page AD9852 ...

Page 28

AD9852 USING THE AD9852 INTERNAL AND EXTERNAL UPDATE CLOCK The update clock function is comprised of a bidirectional I/O UD CLK pin, Pin 20, and a programmable 32-bit down- counter. In order for programming changes to be transferred from the ...

Page 29

The two fixed elements of the transition time are the period of the system clock (which drives the ramp-rate counter) and the number of amplitude steps (4096). For example, assume the system clock of the AD9852 is 100 MHz (10 ...

Page 30

AD9852 COSINE DAC The cosine output of the DDS drives the cosine DAC (300 MSPS maximum). Its maximum output amplitude is set by the DAC R resistor at Pin 56. This is a current-output DAC with a full-scale maximum output ...

Page 31

PLL Filter The PLL FILTER pin, Pin 61, provides the connection for the external zero compensation network of the PLL loop filter. The zero compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF capacitor. The ...

Page 32

AD9852 PROGRAMMING THE AD9852 The AD9852 Register Layout table (Table 8) contains information for programming a chip for a desired functionality. While many applications require very little programming to configure the AD9852, some make use of all 12 accessible register ...

Page 33

Shaded sections comprise the control register. Table 8. Register Layout Parallel Serial Address Address (Hex) (Hex) Bit Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care) 01 Phase Adjust Register 1 <7:0> Phase Adjust ...

Page 34

AD9852 A<5:0> A1 D<7:0> RDHOZ T AHD SPECIFICATION T ADV T AHD T RDLOV T RDHOZ A<5:0> A1 D<7:0> WRHIGH SPECIFICATION T ASU T DSU T ADH T DHD T WRLOW T WRHIGH T ...

Page 35

GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a serial communication cycle with the AD9852. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9852, coincident with the first eight ...

Page 36

AD9852 SERIAL INTERFACE PORT PIN DESCRIPTIONS Table 11. Pin Description SCLK Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state machines. SCLK maximum frequency is ...

Page 37

CONTROL REGISTER DESCRIPTIONS The control register is located at Address 1D hex to Address 20 hex, shown in the shaded portion of Table composed of 32 bits. Bit 31 is located at the top left position, and ...

Page 38

AD9852 INSTRUCTION CYCLE CS SCLK SDIO INSTRUCTION CYCLE CS SCLK SDIO SDO INSTRUCTION CYCLE CS SCLK SDIO INSTRUCTION CYCLE CS SCLK SDIO ...

Page 39

... Given that the junction temperature should never exceed 150°C for the AD9852 and that the ambient temperature can be 85°C, the maximum power consumption is 1.7 W for the AD9852AST and 4.1 W for the AD9852ASQ (thermally enhanced package). Factors affecting the power dissipation are described is the Supply Voltage section. ...

Page 40

AD9852 As can be seen in Figure 60, the inverse sinc filter function requires a significant amount of power alternative approach to maintaining flatness across the output bandwidth, the digital multiplier function can be used to adjust the ...

Page 41

... THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES This section gives general recommendations for mounting the thermally enhanced exposed heat sink package (AD9852ASQ) to printed circuit boards. The exceptional thermal character- istics of this package depend entirely on proper mechanical attachment. ...

Page 42

AD9852 The thermal land itself must be able to distribute heat to an even larger copper plane, such as an internal ground plane. Vias must be uniformly provided over the entire thermal pad to connect to this internal plane. A ...

Page 43

... EVALUATION BOARD INSTRUCTIONS The AD9852/AD9854 Rev. E evaluation board includes either an AD9852ASQ or AD9854ASQ IC. The ASQ package permits 300 MHz operation by virtue of its thermally enhanced design. This package has a bottom-side heat slug that must be soldered to the ground plane of the PCB directly beneath the IC ...

Page 44

AD9852 Programming and ADI software are not used to program the AD9852, Headers W9, W11, W12, W13, W14, and W15 should be opened (shorting jumpers removed). This effectively detaches the PC interface and allows J10 (the 40-pin ...

Page 45

This additional step reroutes the filtered signals away from their output connectors (J6 and J7) and to the 100 Ω configured comparator inputs. This sets up the comparator for differential input without control of the comparator output duty cycle. The ...

Page 46

... AD9852 Table 14. AD9852/AD9854 Customer Evaluation Board (AD9852 PCB > AD9852ASQ, AD9854 PCB > AD9854ASQ) Number Quantity REFDES 1 3 C1, C2, C45 2 21 C7, C8, C9, C10, C11, C12, C13, C14, C16, C17, C18, C19, C20, C22, C23, C24, C26, C27, C28, C29, C44 3 2 C4, C37 4 2 C5, C38 ...

Page 47

PLLFLT GND3 NC5 DIFFCLKEN AVDD CLKVDD CLKGND GND4 REFCLK CLK8 CLK REFCLK PMODE SPSELECT RESET MRESET OPTGND DVDD6 DVDD DVDD7 DGND6 DGND7 DGND8 DGND9 DVDD DVDD8 DVDD9 COUTGND2 GND COUTGND GND COUTVDD2 AVDD COUTVDD AVDD VOUT NC2 DACDGND2 GND DACDGND ...

Page 48

AD9852 Figure 66. Evaluation Board Schematic Rev Page ...

Page 49

Figure 67. Assembly Drawing Figure 68. Top Routing Layer, Layer 1 Rev Page AD9852 ...

Page 50

AD9852 Figure 69. Ground Plane Layer, Layer 2 Figure 70. Power Plane Layer, Layer 3 Rev Page ...

Page 51

Figure 71. Bottom Routing Layer, Layer 4 Rev Page AD9852 ...

Page 52

... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9852ASQ –40°C to +85°C 1 AD9852ASQZ –40°C to +85°C AD9852AST –40°C to +85°C 1 AD9852ASTZ –40°C to +85°C AD9852/PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00634– ...

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