IS43DR16320B-37CBLI ISSI, Integrated Silicon Solution Inc, IS43DR16320B-37CBLI Datasheet - Page 7

• Manufacturer Part Number: IS43DR16320B-37CBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16320B-37CBLI

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

IS43/46DR86400B, IS43/46DR16320B
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal
operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically
re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur
before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait
for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
Extended Mode Register 1(EMR[1]) Diagram
Notes:
1.
2.
3.
4.
DDR2 Extended Mode Register 2 (EMR[2]) Setting
The extended mode register 2 controls refresh related features. The default value of the extended mode register 2 is not defined.
Therefore, the extended mode register must be programmed during initialization for proper operation. The extended mode register
2 is written by asserting LOW on CS, RAS, CAS, WE, BA0, and HIGH on BA1, while controlling pins A0-A13. The DDR2 SDRAM should
be in all bank precharge state with CKE already HIGH prior to writing into extended mode register 2. The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register 2. Mode register contents can
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
Address
A13
Field
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A13 is reserved for future use and must be set to 0 when programming the EMR[1].
If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don’t care for writes. The x16 option does not support RDQS. This must be set to 0
when programming the EMR[1] for the x16 option.
When Adjust mode is issued, AL from previously set value must be applied.
After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.
(1)
Program
Register
Additive
Latency
Mode
RDQS
DQS#
Qoff
OCD
D.I.C
DLL
Rtt
Rtt
0
1
0
A11
A12
A10
A9
A5
A1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
(2)
A8
A4
RDQS Enable
0
0
1
0
1
0
0
1
1
0
0
1
1
Output buffer enabled
Ouput buffer disabled
Output Drive Impedance Control
Disable
Disable
Enable
Enable
DQS#
Normal Strength (100%)
Reduced strength (60%)
Qoff
A7
A3
0
1
0
0
1
0
1
0
1
0
1
0
1
(RDQS)
Additive Latency
A11
0
0
1
1
OCD Calibration mode exit; maintain setting
Reserved
Reserved
0
1
2
3
4
5
(DQS#)
A10
OCD Calibration default
OCD Calibration Program
0
1
0
1
Adjust mode
RDQS/DM
Drive(1)
Drive(0)
RDQS
RDQS
DM
DM
Strobe Function Matrix
(3)
RDQS#
RDQS#
Hi-Z
Hi-Z
Hi-Z
A6
A0
(4)
0
0
1
1
0
1
DQS
DQS
DQS
DQS
DQS
A2
0
1
0
1
DLL enable
Disable
Enable
DQS#
DQS#
DQS#
Hi-Z
Hi-Z
Rtt(NOMINAL)
ODT Disabled
150 ohms
75 ohms
50 ohms
7